| Message ID | 1407109631-5470-2-git-send-email-marex@denx.de |
|---|---|
| State | Awaiting Upstream |
| Delegated to: | Stefano Babic |
| Headers | show |
On Sun, Aug 3, 2014 at 4:47 PM, Marek Vasut <marex@denx.de> wrote: > The MX6 DRAM controller can be configured to handle 4GiB of DRAM, but > only 3840 MiB of that can be really used. In case the controller is > configured to operate a 4GiB module, the imx_ddr_size() function will > correctly compute that there is 4GiB of DRAM in the system. Firstly, > the return value is 32-bit, so the function will effectively return > zero. Secondly, the MX6 cannot address the full 4GiB, but only 3840MiB > of all that. Thus, clamp the returned size to 3840MiB in such case. > > Signed-off-by: Marek Vasut <marex@denx.de> > --- > arch/arm/imx-common/cpu.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c > index 5a09107..0ec8b18 100644 > --- a/arch/arm/imx-common/cpu.c > +++ b/arch/arm/imx-common/cpu.c > @@ -93,6 +93,11 @@ unsigned imx_ddr_size(void) > bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)]; > bits += ESD_MMDC_CTL_GET_WIDTH(ctl); > bits += ESD_MMDC_CTL_GET_CS1(ctl); > + > + /* The MX6 can do only 3840 MiB of DRAM */ > + if (bits == 32) > + return 0xf0000000; > + > return 1 << bits; > } > #endif > -- > 2.0.1 > Acked-by: Tim Harvey <tharvey@gateworks.com> Tim
On 04/08/2014 01:47, Marek Vasut wrote: > The MX6 DRAM controller can be configured to handle 4GiB of DRAM, but > only 3840 MiB of that can be really used. In case the controller is > configured to operate a 4GiB module, the imx_ddr_size() function will > correctly compute that there is 4GiB of DRAM in the system. Firstly, > the return value is 32-bit, so the function will effectively return > zero. Secondly, the MX6 cannot address the full 4GiB, but only 3840MiB > of all that. Thus, clamp the returned size to 3840MiB in such case. > > Signed-off-by: Marek Vasut <marex@denx.de> > --- Applied to u-boot-imx, thanks ! Best regards, Stefano Babic
diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 5a09107..0ec8b18 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -93,6 +93,11 @@ unsigned imx_ddr_size(void) bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)]; bits += ESD_MMDC_CTL_GET_WIDTH(ctl); bits += ESD_MMDC_CTL_GET_CS1(ctl); + + /* The MX6 can do only 3840 MiB of DRAM */ + if (bits == 32) + return 0xf0000000; + return 1 << bits; } #endif
The MX6 DRAM controller can be configured to handle 4GiB of DRAM, but only 3840 MiB of that can be really used. In case the controller is configured to operate a 4GiB module, the imx_ddr_size() function will correctly compute that there is 4GiB of DRAM in the system. Firstly, the return value is 32-bit, so the function will effectively return zero. Secondly, the MX6 cannot address the full 4GiB, but only 3840MiB of all that. Thus, clamp the returned size to 3840MiB in such case. Signed-off-by: Marek Vasut <marex@denx.de> --- arch/arm/imx-common/cpu.c | 5 +++++ 1 file changed, 5 insertions(+)