diff mbox series

[for-4.0] target/i386: Generate #UD for LOCK on a register increment

Message ID 20190328104750.25046-1-peter.maydell@linaro.org
State New
Headers show
Series [for-4.0] target/i386: Generate #UD for LOCK on a register increment | expand

Commit Message

Peter Maydell March 28, 2019, 10:47 a.m. UTC
Fix a TCG crash due to attempting an atomic increment
operation without having set up the address first.
This is a similar case to that dealt with in commit
e84fcd7f662a0d8198703, and we fix it in the same way.

Fixes: https://bugs.launchpad.net/qemu/+bug/1807675
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/i386/translate.c | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Paolo Bonzini March 28, 2019, 11:14 a.m. UTC | #1
On 28/03/19 11:47, Peter Maydell wrote:
> Fix a TCG crash due to attempting an atomic increment
> operation without having set up the address first.
> This is a similar case to that dealt with in commit
> e84fcd7f662a0d8198703, and we fix it in the same way.
> 
> Fixes: https://bugs.launchpad.net/qemu/+bug/1807675
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  target/i386/translate.c | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/target/i386/translate.c b/target/i386/translate.c
> index 49cd298374b..b725bec37cd 100644
> --- a/target/i386/translate.c
> +++ b/target/i386/translate.c
> @@ -1398,6 +1398,11 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
>  static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c)
>  {
>      if (s1->prefix & PREFIX_LOCK) {
> +        if (d != OR_TMP0) {
> +            /* Lock prefix when destination is not memory */
> +            gen_illegal_opcode(s1);
> +            return;
> +        }
>          tcg_gen_movi_tl(s1->T0, c > 0 ? 1 : -1);
>          tcg_gen_atomic_add_fetch_tl(s1->T0, s1->A0, s1->T0,
>                                      s1->mem_index, ot | MO_LE);
> 

Acked-by: Paolo Bonzini <pbonzini@redhat.com>

Feel free to apply it yourself.

Paolo
Peter Maydell April 9, 2019, 1:10 p.m. UTC | #2
On Thu, 28 Mar 2019 at 11:14, Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> On 28/03/19 11:47, Peter Maydell wrote:
> > Fix a TCG crash due to attempting an atomic increment
> > operation without having set up the address first.
> > This is a similar case to that dealt with in commit
> > e84fcd7f662a0d8198703, and we fix it in the same way.
> >
> > Fixes: https://bugs.launchpad.net/qemu/+bug/1807675
> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> > ---
> >  target/i386/translate.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/target/i386/translate.c b/target/i386/translate.c
> > index 49cd298374b..b725bec37cd 100644
> > --- a/target/i386/translate.c
> > +++ b/target/i386/translate.c
> > @@ -1398,6 +1398,11 @@ static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
> >  static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c)
> >  {
> >      if (s1->prefix & PREFIX_LOCK) {
> > +        if (d != OR_TMP0) {
> > +            /* Lock prefix when destination is not memory */
> > +            gen_illegal_opcode(s1);
> > +            return;
> > +        }
> >          tcg_gen_movi_tl(s1->T0, c > 0 ? 1 : -1);
> >          tcg_gen_atomic_add_fetch_tl(s1->T0, s1->A0, s1->T0,
> >                                      s1->mem_index, ot | MO_LE);
> >
>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
>
> Feel free to apply it yourself.

Applied to master, thanks.

-- PMM
diff mbox series

Patch

diff --git a/target/i386/translate.c b/target/i386/translate.c
index 49cd298374b..b725bec37cd 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -1398,6 +1398,11 @@  static void gen_op(DisasContext *s1, int op, TCGMemOp ot, int d)
 static void gen_inc(DisasContext *s1, TCGMemOp ot, int d, int c)
 {
     if (s1->prefix & PREFIX_LOCK) {
+        if (d != OR_TMP0) {
+            /* Lock prefix when destination is not memory */
+            gen_illegal_opcode(s1);
+            return;
+        }
         tcg_gen_movi_tl(s1->T0, c > 0 ? 1 : -1);
         tcg_gen_atomic_add_fetch_tl(s1->T0, s1->A0, s1->T0,
                                     s1->mem_index, ot | MO_LE);