@@ -116,8 +116,16 @@ (define_predicate "vlogical_operand"
;; Return 1 if op is the carry register.
(define_predicate "ca_operand"
- (and (match_code "reg")
- (match_test "CA_REGNO_P (REGNO (op))")))
+ (match_operand 0 "register_operand")
+{
+ if (GET_CODE (op) == SUBREG)
+ op = SUBREG_REG (op);
+
+ if (!REG_P (op))
+ return 0;
+
+ return CA_REGNO_P (REGNO (op));
+})
;; Return 1 if op is a signed 5-bit constant integer.
(define_predicate "s5bit_cint_operand"
@@ -1121,6 +1129,10 @@ (define_predicate "input_operand"
|| GET_MODE_SIZE (mode) > UNITS_PER_WORD)
return register_operand (op, mode);
+ /* We don't allow moving the carry bit around. */
+ if (ca_operand (op, mode))
+ return 0;
+
/* The only cases left are integral modes one word or smaller (we
do not get called for MODE_CC values). These can be in any
register. */
@@ -1780,7 +1780,7 @@ rs6000_hard_regno_mode_ok (int regno, enum machine_mode mode)
return GET_MODE_CLASS (mode) == MODE_CC;
if (CA_REGNO_P (regno))
- return mode == BImode;
+ return mode == Pmode || mode == SImode;
/* AltiVec only in AldyVec registers. */
if (ALTIVEC_REGNO_P (regno))
@@ -2475,7 +2475,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
- rs6000_regno_regclass[CA_REGNO] = CA_REGS;
+ rs6000_regno_regclass[CA_REGNO] = NO_REGS;
rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
rs6000_regno_regclass[SPE_ACC_REGNO] = SPE_ACC_REGS;