| Message ID | 20211008163640.1753821-1-miquel.raynal@bootlin.com |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [v2] mtd: rawnand: arasan: Prevent an unsupported configuration | expand |
On Fri, 2021-10-08 at 16:36:40 UTC, Miquel Raynal wrote: > Under the following conditions: > * after rounding up by 4 the number of bytes to transfer (this is > related to the controller's internal constraints), > * if this (rounded) amount of data is situated beyond the end of the > device, > * and only in NV-DDR mode, > the Arasan NAND controller timeouts. > > This currently can happen in a particular helper used when picking > software ECC algorithms. Let's prevent this situation by refusing to use > the NV-DDR interface with software engines. > > Fixes: 4edde6031458 ("mtd: rawnand: arasan: Support NV-DDR interface") > Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next. Miquel
diff --git a/drivers/mtd/nand/raw/arasan-nand-controller.c b/drivers/mtd/nand/raw/arasan-nand-controller.c index 9cbcc698c64d..53bd10738418 100644 --- a/drivers/mtd/nand/raw/arasan-nand-controller.c +++ b/drivers/mtd/nand/raw/arasan-nand-controller.c @@ -973,6 +973,21 @@ static int anfc_setup_interface(struct nand_chip *chip, int target, nvddr = nand_get_nvddr_timings(conf); if (IS_ERR(nvddr)) return PTR_ERR(nvddr); + + /* + * The controller only supports data payload requests which are + * a multiple of 4. In practice, most data accesses are 4-byte + * aligned and this is not an issue. However, rounding up will + * simply be refused by the controller if we reached the end of + * the device *and* we are using the NV-DDR interface(!). In + * this situation, unaligned data requests ending at the device + * boundary will confuse the controller and cannot be performed. + * + * This is something that happens in nand_read_subpage() when + * selecting software ECC support and must be avoided. + */ + if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT) + return -ENOTSUPP; } else { sdr = nand_get_sdr_timings(conf); if (IS_ERR(sdr))
Under the following conditions: * after rounding up by 4 the number of bytes to transfer (this is related to the controller's internal constraints), * if this (rounded) amount of data is situated beyond the end of the device, * and only in NV-DDR mode, the Arasan NAND controller timeouts. This currently can happen in a particular helper used when picking software ECC algorithms. Let's prevent this situation by refusing to use the NV-DDR interface with software engines. Fixes: 4edde6031458 ("mtd: rawnand: arasan: Support NV-DDR interface") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> --- Changes in v2: As v1 was too invasive Boris suggested to adopt a much simpler approach: let's just avoid the situation. That's what I am doing here. drivers/mtd/nand/raw/arasan-nand-controller.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+)