diff mbox series

[11/18] ARC: mm: move MMU specific bits out of entry code

Message ID 20210811004258.138075-12-vgupta@kernel.org
State New
Headers show
Series ARC mm updates to support 3 or 4 levels of paging | expand

Commit Message

Vineet Gupta Aug. 11, 2021, 12:42 a.m. UTC
Signed-off-by: Vineet Gupta <vgupta@kernel.org>
---
 arch/arc/kernel/entry.S | 6 ------
 arch/arc/mm/tlb.c       | 3 +++
 2 files changed, 3 insertions(+), 6 deletions(-)

Comments

Mike Rapoport Aug. 11, 2021, 12:15 p.m. UTC | #1
I believe a few words here would be useful even for the future version of
yourself ;-)

On Tue, Aug 10, 2021 at 05:42:51PM -0700, Vineet Gupta wrote:
> Signed-off-by: Vineet Gupta <vgupta@kernel.org>
> ---
>  arch/arc/kernel/entry.S | 6 ------
>  arch/arc/mm/tlb.c       | 3 +++
>  2 files changed, 3 insertions(+), 6 deletions(-)
> 
> diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S
> index 2cb8dfe866b6..684efd094520 100644
> --- a/arch/arc/kernel/entry.S
> +++ b/arch/arc/kernel/entry.S
> @@ -101,12 +101,6 @@ ENTRY(EV_MachineCheck)
>  	lr  r0, [efa]
>  	mov r1, sp
>  
> -	; hardware auto-disables MMU, re-enable it to allow kernel vaddr
> -	; access for say stack unwinding of modules for crash dumps
> -	lr	r3, [ARC_REG_PID]
> -	or	r3, r3, MMU_ENABLE
> -	sr	r3, [ARC_REG_PID]
> -
>  	lsr  	r3, r2, 8
>  	bmsk 	r3, r3, 7
>  	brne    r3, ECR_C_MCHK_DUP_TLB, 1f
> diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
> index b68d5798327b..34f16e0b41e6 100644
> --- a/arch/arc/mm/tlb.c
> +++ b/arch/arc/mm/tlb.c
> @@ -813,5 +813,8 @@ void do_tlb_overlap_fault(unsigned long cause, unsigned long address,
>  		}
>  	}
>  
> +	/* Re-enable MMU as hardware may have auto-disabled it upon exception */
> +	write_aux_reg(ARC_REG_PID, read_aux_reg(ARC_REG_PID) | MMU_ENABLE);
> +
>  	local_irq_restore(flags);
>  }
> -- 
> 2.25.1
>
Vineet Gupta Aug. 11, 2021, 7:30 p.m. UTC | #2
On 8/11/21 5:15 AM, Mike Rapoport wrote:
> I believe a few words here would be useful even for the future version of
> yourself ;-)

"Don't pollute common entry file with MMU versions specific bits (as new 
MMU doesn't have PID register)"

However Jose thankfully pointed me (off list) that this patch is broken 
(based on some internal emails).
Any Machine check disables MMU but we now we only re-enable for TLB 
faults related MC, so this will have to be redone.

Thx,
-Vineet
diff mbox series

Patch

diff --git a/arch/arc/kernel/entry.S b/arch/arc/kernel/entry.S
index 2cb8dfe866b6..684efd094520 100644
--- a/arch/arc/kernel/entry.S
+++ b/arch/arc/kernel/entry.S
@@ -101,12 +101,6 @@  ENTRY(EV_MachineCheck)
 	lr  r0, [efa]
 	mov r1, sp
 
-	; hardware auto-disables MMU, re-enable it to allow kernel vaddr
-	; access for say stack unwinding of modules for crash dumps
-	lr	r3, [ARC_REG_PID]
-	or	r3, r3, MMU_ENABLE
-	sr	r3, [ARC_REG_PID]
-
 	lsr  	r3, r2, 8
 	bmsk 	r3, r3, 7
 	brne    r3, ECR_C_MCHK_DUP_TLB, 1f
diff --git a/arch/arc/mm/tlb.c b/arch/arc/mm/tlb.c
index b68d5798327b..34f16e0b41e6 100644
--- a/arch/arc/mm/tlb.c
+++ b/arch/arc/mm/tlb.c
@@ -813,5 +813,8 @@  void do_tlb_overlap_fault(unsigned long cause, unsigned long address,
 		}
 	}
 
+	/* Re-enable MMU as hardware may have auto-disabled it upon exception */
+	write_aux_reg(ARC_REG_PID, read_aux_reg(ARC_REG_PID) | MMU_ENABLE);
+
 	local_irq_restore(flags);
 }