| Message ID | 20210528214522.617435-1-sean.anderson@seco.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v4,1/3] dt-bindings: pwm: Add Xilinx AXI Timer | expand |
On Fri, 28 May 2021 17:45:20 -0400, Sean Anderson wrote: > This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is > a "soft" block, so it has many parameters which would not be > configurable in most hardware. This binding is usually automatically > generated by Xilinx's tools, so the names and values of some properties > must be kept as they are. Replacement properties have been provided for > new device trees. > > Because we need to init timer devices so early in boot, the easiest way > to configure things is to use a device tree property. For the moment > this is 'xlnx,pwm', but this could be extended/renamed/etc. in the > future if these is a need for a generic property. > > Signed-off-by: Sean Anderson <sean.anderson@seco.com> > --- > > Changes in v4: > - Remove references to generate polarity so this can get merged > - Predicate PWM driver on the presence of #pwm-cells > - Make some properties optional for clocksource drivers > > Changes in v3: > - Mark all boolean-as-int properties as deprecated > - Add xlnx,pwm and xlnx,gen?-active-low properties. > - Make newer replacement properties mutually-exclusive with what they > replace > - Add an example with non-deprecated properties only. > > Changes in v2: > - Use 32-bit addresses for example binding > > .../bindings/pwm/xlnx,axi-timer.yaml | 85 +++++++++++++++++++ > 1 file changed, 85 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: ./Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml:16:10: [warning] wrong indentation: expected 10 but found 9 (indentation) ./Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml:19:10: [warning] wrong indentation: expected 10 but found 9 (indentation) dtschema/dtc warnings/errors: See https://patchwork.ozlabs.org/patch/1485318 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
On 6/1/21 9:32 AM, Rob Herring wrote: > On Fri, 28 May 2021 17:45:20 -0400, Sean Anderson wrote: >> This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is >> a "soft" block, so it has many parameters which would not be >> configurable in most hardware. This binding is usually automatically >> generated by Xilinx's tools, so the names and values of some properties >> must be kept as they are. Replacement properties have been provided for >> new device trees. >> >> Because we need to init timer devices so early in boot, the easiest way >> to configure things is to use a device tree property. For the moment >> this is 'xlnx,pwm', but this could be extended/renamed/etc. in the >> future if these is a need for a generic property. >> >> Signed-off-by: Sean Anderson <sean.anderson@seco.com> >> --- >> >> Changes in v4: >> - Remove references to generate polarity so this can get merged >> - Predicate PWM driver on the presence of #pwm-cells >> - Make some properties optional for clocksource drivers >> >> Changes in v3: >> - Mark all boolean-as-int properties as deprecated >> - Add xlnx,pwm and xlnx,gen?-active-low properties. >> - Make newer replacement properties mutually-exclusive with what they >> replace >> - Add an example with non-deprecated properties only. >> >> Changes in v2: >> - Use 32-bit addresses for example binding >> >> .../bindings/pwm/xlnx,axi-timer.yaml | 85 +++++++++++++++++++ >> 1 file changed, 85 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >> > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > ./Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml:16:10: [warning] wrong indentation: expected 10 but found 9 (indentation) > ./Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml:19:10: [warning] wrong indentation: expected 10 but found 9 (indentation) > > dtschema/dtc warnings/errors: > > See https://patchwork.ozlabs.org/patch/1485318 > > This check can fail if there are any dependencies. The base for a patch > series is generally the most recent rc1. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: I needed yamllint installed to get these errors. Is this requirement documented anywhere? I don't see it in [1]. --Sean [1] https://www.kernel.org/doc/html/latest/devicetree/bindings/writing-schema.html#testing > > pip3 install dtschema --upgrade > > Please check and re-submit. >
Hello Sean, I wonder what tree you chose as a base here. I found tags/v5.13-rc1~44^2 as a tree that your patches can be applied to (and tags/v5.13-rc1~44 or later doesn't work). I recommend using git format-patch --base ... . This makes it easier for the responsible maintainers to pick the right base and allows easier automatic testing. Best regards Uwe
On 6/29/21 4:38 AM, Uwe Kleine-König wrote: > Hello Sean, > > I wonder what tree you chose as a base here. I found tags/v5.13-rc1~44^2 > as a tree that your patches can be applied to (and tags/v5.13-rc1~44 or > later doesn't work). I recommend using Hm, looks like it's based off of pwm/for-next from April. I will rebase onto something newer for the next revision. --Sean > > git format-patch --base ... > > . This makes it easier for the responsible maintainers to pick the > right base and allows easier automatic testing. > > Best regards > Uwe >
On 5/28/21 11:45 PM, Sean Anderson wrote: > This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is > a "soft" block, so it has many parameters which would not be > configurable in most hardware. This binding is usually automatically > generated by Xilinx's tools, so the names and values of some properties > must be kept as they are. Replacement properties have been provided for > new device trees. > > Because we need to init timer devices so early in boot, the easiest way > to configure things is to use a device tree property. For the moment > this is 'xlnx,pwm', but this could be extended/renamed/etc. in the > future if these is a need for a generic property. > > Signed-off-by: Sean Anderson <sean.anderson@seco.com> > --- > > Changes in v4: > - Remove references to generate polarity so this can get merged > - Predicate PWM driver on the presence of #pwm-cells > - Make some properties optional for clocksource drivers > > Changes in v3: > - Mark all boolean-as-int properties as deprecated > - Add xlnx,pwm and xlnx,gen?-active-low properties. > - Make newer replacement properties mutually-exclusive with what they > replace > - Add an example with non-deprecated properties only. > > Changes in v2: > - Use 32-bit addresses for example binding > > .../bindings/pwm/xlnx,axi-timer.yaml | 85 +++++++++++++++++++ > 1 file changed, 85 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > > diff --git a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > new file mode 100644 > index 000000000000..48a280f96e63 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml I don't think this is the right location for this. I have done some grepping and I think this should be done in a different way. I pretty much like solution around "ti,omap3430-timer" which is calling dmtimer_systimer_select_best() and later dmtimer_is_preferred() which in this case would allow us to get rid of cases which are not suitable for clocksource and clockevent. And there is drivers/pwm/pwm-omap-dmtimer.c which has link to timer which is providing functions for it's functionality. I have also looked at Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml which is also the same device. And sort of curious if you look at https://www.xilinx.com/support/documentation/ip_documentation/axi_timer/v2_0/pg079-axi-timer.pdf ( Figure 1-1) that PWM is taking input from generate out 0 and generate out 1 which is maybe can be modeled is any output and pwm driver can register inputs for pwm driver. > @@ -0,0 +1,85 @@ > +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pwm/xlnx,axi-timer.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding > + > +maintainers: > + - Sean Anderson <sean.anderson@seco.com> > + > +properties: > + compatible: > + oneOf: > + - items: > + - const: xlnx,axi-timer-2.0 > + - const: xlnx,xps-timer-1.00.a > + - items: > + - const: xlnx,xps-timer-1.00.a > + > + clocks: > + maxItems: 1 > + > + clock-names: > + const: s_axi_aclk Origin driver is not using this clock name and it is only one that's why it shouldn't be listed. > + > + interrupts: > + maxItems: 1 > + > + reg: > + maxItems: 1 > + > + xlnx,count-width: > + $ref: /schemas/types.yaml#/definitions/uint32 > + minimum: 8 > + maximum: 32 > + default: 32 This is not accurate. It should be enum because only 8/16/32 are valid values here. > + description: > + The width of the counter(s), in bits. > + > + xlnx,one-timer-only: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [ 0, 1 ] > + description: > + Whether only one timer is present in this block. > + > +required: > + - compatible > + - reg > + - xlnx,one-timer-only > + > +allOf: > + - if: > + required: > + - '#pwm-cells' Let's discussed this usage based on design. > + then: > + allOf: > + - required: > + - clocks > + - properties: > + xlnx,one-timer-only: > + const: 0 > + else: > + required: > + - interrupts > + - if: > + required: > + - clocks > + then: > + required: > + - clock-names And this checking should be removed too. > + > +additionalProperties: true > + > +examples: > + - | > + axi_timer_0: timer@800e0000 { label is useless here and should be removed. > + #pwm-cells = <0>; > + clock-names = "s_axi_aclk"; > + clocks = <&zynqmp_clk 71>; > + compatible = "xlnx,axi-timer-2.0", "xlnx,xps-timer-1.00.a"; > + reg = <0x800e0000 0x10000>; > + xlnx,count-width = <0x20>; > + xlnx,one-timer-only = <0x0>; > + }; > I would list example without pwm-cells first as it is valid and reflect current status. Thanks, Michal
On 6/30/21 3:47 PM, Michal Simek wrote: > > > On 5/28/21 11:45 PM, Sean Anderson wrote: >> This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is >> a "soft" block, so it has many parameters which would not be >> configurable in most hardware. This binding is usually automatically >> generated by Xilinx's tools, so the names and values of some properties >> must be kept as they are. Replacement properties have been provided for >> new device trees. >> >> Because we need to init timer devices so early in boot, the easiest way >> to configure things is to use a device tree property. For the moment >> this is 'xlnx,pwm', but this could be extended/renamed/etc. in the >> future if these is a need for a generic property. >> >> Signed-off-by: Sean Anderson <sean.anderson@seco.com> >> --- >> >> Changes in v4: >> - Remove references to generate polarity so this can get merged >> - Predicate PWM driver on the presence of #pwm-cells >> - Make some properties optional for clocksource drivers >> >> Changes in v3: >> - Mark all boolean-as-int properties as deprecated >> - Add xlnx,pwm and xlnx,gen?-active-low properties. >> - Make newer replacement properties mutually-exclusive with what they >> replace >> - Add an example with non-deprecated properties only. >> >> Changes in v2: >> - Use 32-bit addresses for example binding >> >> .../bindings/pwm/xlnx,axi-timer.yaml | 85 +++++++++++++++++++ >> 1 file changed, 85 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >> >> diff --git a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >> new file mode 100644 >> index 000000000000..48a280f96e63 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > > I don't think this is the right location for this. > > I have done some grepping and I think this should be done in a different > way. I pretty much like solution around "ti,omap3430-timer" which is > calling dmtimer_systimer_select_best() and later dmtimer_is_preferred() > which in this case would allow us to get rid of cases which are not > suitable for clocksource and clockevent. > > And there is drivers/pwm/pwm-omap-dmtimer.c which has link to timer > which is providing functions for it's functionality. > > I have also looked at > Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml which is also > the same device. > > And sort of curious if you look at > https://www.xilinx.com/support/documentation/ip_documentation/axi_timer/v2_0/pg079-axi-timer.pdf > ( Figure 1-1) > that PWM is taking input from generate out 0 and generate out 1 which is > maybe can be modeled is any output and pwm driver can register inputs > for pwm driver. > > >> @@ -0,0 +1,85 @@ >> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pwm/xlnx,axi-timer.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding >> + >> +maintainers: >> + - Sean Anderson <sean.anderson@seco.com> >> + >> +properties: >> + compatible: >> + oneOf: >> + - items: >> + - const: xlnx,axi-timer-2.0 I am not quite sure if make sense also to list 2.0 version. There were likely also 1.0 version which is compatible with origin xps version which IIRC was PLB based. And the same driver was using in past with OPB bus. Thanks, Michal
On 6/30/21 9:47 AM, Michal Simek wrote: > > > On 5/28/21 11:45 PM, Sean Anderson wrote: >> This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is >> a "soft" block, so it has many parameters which would not be >> configurable in most hardware. This binding is usually automatically >> generated by Xilinx's tools, so the names and values of some properties >> must be kept as they are. Replacement properties have been provided for >> new device trees. >> >> Because we need to init timer devices so early in boot, the easiest way >> to configure things is to use a device tree property. For the moment >> this is 'xlnx,pwm', but this could be extended/renamed/etc. in the >> future if these is a need for a generic property. >> >> Signed-off-by: Sean Anderson <sean.anderson@seco.com> >> --- >> >> Changes in v4: >> - Remove references to generate polarity so this can get merged >> - Predicate PWM driver on the presence of #pwm-cells >> - Make some properties optional for clocksource drivers >> >> Changes in v3: >> - Mark all boolean-as-int properties as deprecated >> - Add xlnx,pwm and xlnx,gen?-active-low properties. >> - Make newer replacement properties mutually-exclusive with what they >> replace >> - Add an example with non-deprecated properties only. >> >> Changes in v2: >> - Use 32-bit addresses for example binding >> >> .../bindings/pwm/xlnx,axi-timer.yaml | 85 +++++++++++++++++++ >> 1 file changed, 85 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >> >> diff --git a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >> new file mode 100644 >> index 000000000000..48a280f96e63 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > > I don't think this is the right location for this. > > I have done some grepping and I think this should be done in a different > way. I pretty much like solution around "ti,omap3430-timer" which is > calling dmtimer_systimer_select_best() and later dmtimer_is_preferred() > which in this case would allow us to get rid of cases which are not > suitable for clocksource and clockevent. > > And there is drivers/pwm/pwm-omap-dmtimer.c which has link to timer > which is providing functions for it's functionality. > > I have also looked at > Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml which is also > the same device. Ok, I will move this under bindings/timer. > > And sort of curious if you look at > https://www.xilinx.com/support/documentation/ip_documentation/axi_timer/v2_0/pg079-axi-timer.pdf > ( Figure 1-1) > that PWM is taking input from generate out 0 and generate out 1 which is > maybe can be modeled is any output and pwm driver can register inputs > for pwm driver. I don't think that is a good model, since several bits (GENERATE, PWM, etc) need to be set in the TCSR, and we need to coordinate changes between timers closely to keep our contract for apply_state(). Although that is how the hardware is organized, the requirements of the clocksource and pwm subsystems are very different. >> @@ -0,0 +1,85 @@ >> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause >> +%YAML 1.2 >> +--- >> +$id: http://devicetree.org/schemas/pwm/xlnx,axi-timer.yaml# >> +$schema: http://devicetree.org/meta-schemas/core.yaml# >> + >> +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding >> + >> +maintainers: >> + - Sean Anderson <sean.anderson@seco.com> >> + >> +properties: >> + compatible: >> + oneOf: >> + - items: >> + - const: xlnx,axi-timer-2.0 >> + - const: xlnx,xps-timer-1.00.a >> + - items: >> + - const: xlnx,xps-timer-1.00.a >> + >> + clocks: >> + maxItems: 1 >> + >> + clock-names: >> + const: s_axi_aclk > > Origin driver is not using this clock name and it is only one that's why > it shouldn't be listed. The old driver does not use the clocks property. So this property is only required for new bindings. Note that if the clocks property is not present, we fall back to clock-frequency, and if that is not present we fall back to /cpus/timebase-frequency. However, these methods are deprecated, so they are not documented here. > >> + >> + interrupts: >> + maxItems: 1 >> + >> + reg: >> + maxItems: 1 >> + >> + xlnx,count-width: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + minimum: 8 >> + maximum: 32 >> + default: 32 > > This is not accurate. It should be enum because only 8/16/32 are valid > values here. According to the datasheet the allowable values are "8-32", so that is what I put. Perhaps it should be updated? > >> + description: >> + The width of the counter(s), in bits. >> + >> + xlnx,one-timer-only: >> + $ref: /schemas/types.yaml#/definitions/uint32 >> + enum: [ 0, 1 ] >> + description: >> + Whether only one timer is present in this block. >> + >> +required: >> + - compatible >> + - reg >> + - xlnx,one-timer-only >> + >> +allOf: >> + - if: >> + required: >> + - '#pwm-cells' > > Let's discussed this usage based on design. I don't understand what you mean by this. > >> + then: >> + allOf: >> + - required: >> + - clocks >> + - properties: >> + xlnx,one-timer-only: >> + const: 0 >> + else: >> + required: >> + - interrupts >> + - if: >> + required: >> + - clocks >> + then: >> + required: >> + - clock-names > > And this checking should be removed too. See above. > >> + >> +additionalProperties: true >> + >> +examples: >> + - | >> + axi_timer_0: timer@800e0000 { > > label is useless here and should be removed. Ok. > >> + #pwm-cells = <0>; >> + clock-names = "s_axi_aclk"; >> + clocks = <&zynqmp_clk 71>; >> + compatible = "xlnx,axi-timer-2.0", "xlnx,xps-timer-1.00.a"; >> + reg = <0x800e0000 0x10000>; >> + xlnx,count-width = <0x20>; >> + xlnx,one-timer-only = <0x0>; >> + }; >> > > I would list example without pwm-cells first as it is valid and reflect > current status. Ok. --Sean
On 6/30/21 9:58 AM, Michal Simek wrote: > > > On 6/30/21 3:47 PM, Michal Simek wrote: >> >> >> On 5/28/21 11:45 PM, Sean Anderson wrote: >>> This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is >>> a "soft" block, so it has many parameters which would not be >>> configurable in most hardware. This binding is usually automatically >>> generated by Xilinx's tools, so the names and values of some properties >>> must be kept as they are. Replacement properties have been provided for >>> new device trees. >>> >>> Because we need to init timer devices so early in boot, the easiest way >>> to configure things is to use a device tree property. For the moment >>> this is 'xlnx,pwm', but this could be extended/renamed/etc. in the >>> future if these is a need for a generic property. >>> >>> Signed-off-by: Sean Anderson <sean.anderson@seco.com> >>> --- >>> >>> Changes in v4: >>> - Remove references to generate polarity so this can get merged >>> - Predicate PWM driver on the presence of #pwm-cells >>> - Make some properties optional for clocksource drivers >>> >>> Changes in v3: >>> - Mark all boolean-as-int properties as deprecated >>> - Add xlnx,pwm and xlnx,gen?-active-low properties. >>> - Make newer replacement properties mutually-exclusive with what they >>> replace >>> - Add an example with non-deprecated properties only. >>> >>> Changes in v2: >>> - Use 32-bit addresses for example binding >>> >>> .../bindings/pwm/xlnx,axi-timer.yaml | 85 +++++++++++++++++++ >>> 1 file changed, 85 insertions(+) >>> create mode 100644 Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >>> >>> diff --git a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >>> new file mode 100644 >>> index 000000000000..48a280f96e63 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >> >> I don't think this is the right location for this. >> >> I have done some grepping and I think this should be done in a different >> way. I pretty much like solution around "ti,omap3430-timer" which is >> calling dmtimer_systimer_select_best() and later dmtimer_is_preferred() >> which in this case would allow us to get rid of cases which are not >> suitable for clocksource and clockevent. >> >> And there is drivers/pwm/pwm-omap-dmtimer.c which has link to timer >> which is providing functions for it's functionality. >> >> I have also looked at >> Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml which is also >> the same device. >> >> And sort of curious if you look at >> https://www.xilinx.com/support/documentation/ip_documentation/axi_timer/v2_0/pg079-axi-timer.pdf >> ( Figure 1-1) >> that PWM is taking input from generate out 0 and generate out 1 which is >> maybe can be modeled is any output and pwm driver can register inputs >> for pwm driver. >> >> >>> @@ -0,0 +1,85 @@ >>> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/pwm/xlnx,axi-timer.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding >>> + >>> +maintainers: >>> + - Sean Anderson <sean.anderson@seco.com> >>> + >>> +properties: >>> + compatible: >>> + oneOf: >>> + - items: >>> + - const: xlnx,axi-timer-2.0 > > I am not quite sure if make sense also to list 2.0 version. > There were likely also 1.0 version which is compatible with origin xps > version which IIRC was PLB based. And the same driver was using in past > with OPB bus. It's required to list all compatible properties which may be used in a binding. And AFAIK it is good practice to add a new compatible string for new releases of an IP, in case incompatibilities are discovered. --Sean
On 7/1/21 5:38 PM, Sean Anderson wrote: > > > On 6/30/21 9:58 AM, Michal Simek wrote: >> >> >> On 6/30/21 3:47 PM, Michal Simek wrote: >>> >>> >>> On 5/28/21 11:45 PM, Sean Anderson wrote: >>>> This adds a binding for the Xilinx LogiCORE IP AXI Timer. This > device is >>>> a "soft" block, so it has many parameters which would not be >>>> configurable in most hardware. This binding is usually automatically >>>> generated by Xilinx's tools, so the names and values of some properties >>>> must be kept as they are. Replacement properties have been provided for >>>> new device trees. >>>> >>>> Because we need to init timer devices so early in boot, the easiest way >>>> to configure things is to use a device tree property. For the moment >>>> this is 'xlnx,pwm', but this could be extended/renamed/etc. in the >>>> future if these is a need for a generic property. >>>> >>>> Signed-off-by: Sean Anderson <sean.anderson@seco.com> >>>> --- >>>> >>>> Changes in v4: >>>> - Remove references to generate polarity so this can get merged >>>> - Predicate PWM driver on the presence of #pwm-cells >>>> - Make some properties optional for clocksource drivers >>>> >>>> Changes in v3: >>>> - Mark all boolean-as-int properties as deprecated >>>> - Add xlnx,pwm and xlnx,gen?-active-low properties. >>>> - Make newer replacement properties mutually-exclusive with what they >>>> replace >>>> - Add an example with non-deprecated properties only. >>>> >>>> Changes in v2: >>>> - Use 32-bit addresses for example binding >>>> >>>> .../bindings/pwm/xlnx,axi-timer.yaml | 85 +++++++++++++++++++ >>>> 1 file changed, 85 insertions(+) >>>> create mode 100644 > Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >>>> >>>> diff --git > a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >>>> new file mode 100644 >>>> index 000000000000..48a280f96e63 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >>> >>> I don't think this is the right location for this. >>> >>> I have done some grepping and I think this should be done in a different >>> way. I pretty much like solution around "ti,omap3430-timer" which is >>> calling dmtimer_systimer_select_best() and later dmtimer_is_preferred() >>> which in this case would allow us to get rid of cases which are not >>> suitable for clocksource and clockevent. >>> >>> And there is drivers/pwm/pwm-omap-dmtimer.c which has link to timer >>> which is providing functions for it's functionality. >>> >>> I have also looked at >>> Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml which is also >>> the same device. >>> >>> And sort of curious if you look at >>> > https://www.xilinx.com/support/documentation/ip_documentation/axi_timer/v2_0/pg079-axi-timer.pdf > >>> ( Figure 1-1) >>> that PWM is taking input from generate out 0 and generate out 1 which is >>> maybe can be modeled is any output and pwm driver can register inputs >>> for pwm driver. >>> >>> >>>> @@ -0,0 +1,85 @@ >>>> +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause >>>> +%YAML 1.2 >>>> +--- >>>> +$id: http://devicetree.org/schemas/pwm/xlnx,axi-timer.yaml# >>>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>>> + >>>> +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding >>>> + >>>> +maintainers: >>>> + - Sean Anderson <sean.anderson@seco.com> >>>> + >>>> +properties: >>>> + compatible: >>>> + oneOf: >>>> + - items: >>>> + - const: xlnx,axi-timer-2.0 >> >> I am not quite sure if make sense also to list 2.0 version. >> There were likely also 1.0 version which is compatible with origin xps >> version which IIRC was PLB based. And the same driver was using in past >> with OPB bus. > > It's required to list all compatible properties which may be used in a > binding. And AFAIK it is good practice to add a new compatible string > for new releases of an IP, in case incompatibilities are discovered. I generally agree with this but is it practical right now if we don't have these incompatibilities. Right now we have 2.0 but there were 1.03.a/1.02.a/1.01a variants just for axi. In past there were variants for PLB and OPB. https://www.xilinx.com/support/documentation/ip_documentation/axi_timer/v1_03_a/pg079-axi-timer.pdf https://www.xilinx.com/support/documentation/ip_documentation/axi_timer/v1_02_a/axi_timer_ds764.pdf https://japan.xilinx.com/support/documentation/ip_documentation/axi_timer_ds764.pdf That's not big problem but seem to me not practical to keep updating bindings docs when new version will be coming just to be listed without any code behind it. We have that versions which is definitely great that if something happens we can add it. But listed all combinations? I am not convinced about it. Thanks, Michal
On 7/1/21 5:32 PM, Sean Anderson wrote: > > > On 6/30/21 9:47 AM, Michal Simek wrote: >> >> >> On 5/28/21 11:45 PM, Sean Anderson wrote: >>> This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is >>> a "soft" block, so it has many parameters which would not be >>> configurable in most hardware. This binding is usually automatically >>> generated by Xilinx's tools, so the names and values of some properties >>> must be kept as they are. Replacement properties have been provided for >>> new device trees. >>> >>> Because we need to init timer devices so early in boot, the easiest way >>> to configure things is to use a device tree property. For the moment >>> this is 'xlnx,pwm', but this could be extended/renamed/etc. in the >>> future if these is a need for a generic property. >>> >>> Signed-off-by: Sean Anderson <sean.anderson@seco.com> >>> --- >>> >>> Changes in v4: >>> - Remove references to generate polarity so this can get merged >>> - Predicate PWM driver on the presence of #pwm-cells >>> - Make some properties optional for clocksource drivers >>> >>> Changes in v3: >>> - Mark all boolean-as-int properties as deprecated >>> - Add xlnx,pwm and xlnx,gen?-active-low properties. >>> - Make newer replacement properties mutually-exclusive with what they >>> replace >>> - Add an example with non-deprecated properties only. >>> >>> Changes in v2: >>> - Use 32-bit addresses for example binding >>> >>> .../bindings/pwm/xlnx,axi-timer.yaml | 85 +++++++++++++++++++ >>> 1 file changed, 85 insertions(+) >>> create mode 100644 > Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >>> >>> diff --git > a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml > b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >>> new file mode 100644 >>> index 000000000000..48a280f96e63 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >> >> I don't think this is the right location for this. >> >> I have done some grepping and I think this should be done in a different >> way. I pretty much like solution around "ti,omap3430-timer" which is >> calling dmtimer_systimer_select_best() and later dmtimer_is_preferred() >> which in this case would allow us to get rid of cases which are not >> suitable for clocksource and clockevent. >> >> And there is drivers/pwm/pwm-omap-dmtimer.c which has link to timer >> which is providing functions for it's functionality. >> >> I have also looked at >> Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml which is also >> the same device. > > Ok, I will move this under bindings/timer. > >> >> And sort of curious if you look at >> > https://www.xilinx.com/support/documentation/ip_documentation/axi_timer/v2_0/pg079-axi-timer.pdf > >> ( Figure 1-1) >> that PWM is taking input from generate out 0 and generate out 1 which is >> maybe can be modeled is any output and pwm driver can register inputs >> for pwm driver. > > I don't think that is a good model, since several bits (GENERATE, PWM, > etc) need to be set in the TCSR, and we need to coordinate changes > between timers closely to keep our contract for apply_state(). Although > that is how the hardware is organized, the requirements of the > clocksource and pwm subsystems are very different. There is another upstream solution done by samsung. Where they use samsung,pwm-outputs property to identify PWMs. I think that make sense to consider to identify which timer should be clocksource/clockevent because with MB SMP this has to be done to pair timer with cpu for clockevents. You can see drivers here. drivers/clocksource/smasung_pwm_timer.c drivers/pwm/pwm-samsung.c Uwe: How does it sound to you? Thanks, Michal
On 7/2/21 8:40 AM, Michal Simek wrote: > > > On 7/1/21 5:32 PM, Sean Anderson wrote: >> >> >> On 6/30/21 9:47 AM, Michal Simek wrote: >>> >>> >>> On 5/28/21 11:45 PM, Sean Anderson wrote: >>>> This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is >>>> a "soft" block, so it has many parameters which would not be >>>> configurable in most hardware. This binding is usually automatically >>>> generated by Xilinx's tools, so the names and values of some properties >>>> must be kept as they are. Replacement properties have been provided for >>>> new device trees. >>>> >>>> Because we need to init timer devices so early in boot, the easiest way >>>> to configure things is to use a device tree property. For the moment >>>> this is 'xlnx,pwm', but this could be extended/renamed/etc. in the >>>> future if these is a need for a generic property. >>>> >>>> Signed-off-by: Sean Anderson <sean.anderson@seco.com> >>>> --- >>>> >>>> Changes in v4: >>>> - Remove references to generate polarity so this can get merged >>>> - Predicate PWM driver on the presence of #pwm-cells >>>> - Make some properties optional for clocksource drivers >>>> >>>> Changes in v3: >>>> - Mark all boolean-as-int properties as deprecated >>>> - Add xlnx,pwm and xlnx,gen?-active-low properties. >>>> - Make newer replacement properties mutually-exclusive with what they >>>> replace >>>> - Add an example with non-deprecated properties only. >>>> >>>> Changes in v2: >>>> - Use 32-bit addresses for example binding >>>> >>>> .../bindings/pwm/xlnx,axi-timer.yaml | 85 +++++++++++++++++++ >>>> 1 file changed, 85 insertions(+) >>>> create mode 100644 >> Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >>>> >>>> diff --git >> a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >> b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >>>> new file mode 100644 >>>> index 000000000000..48a280f96e63 >>>> --- /dev/null >>>> +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml >>> >>> I don't think this is the right location for this. >>> >>> I have done some grepping and I think this should be done in a different >>> way. I pretty much like solution around "ti,omap3430-timer" which is >>> calling dmtimer_systimer_select_best() and later dmtimer_is_preferred() >>> which in this case would allow us to get rid of cases which are not >>> suitable for clocksource and clockevent. >>> >>> And there is drivers/pwm/pwm-omap-dmtimer.c which has link to timer >>> which is providing functions for it's functionality. >>> >>> I have also looked at >>> Documentation/devicetree/bindings/timer/nxp,tpm-timer.yaml which is also >>> the same device. >> >> Ok, I will move this under bindings/timer. >> >>> >>> And sort of curious if you look at >>> >> https://www.xilinx.com/support/documentation/ip_documentation/axi_timer/v2_0/pg079-axi-timer.pdf >> >>> ( Figure 1-1) >>> that PWM is taking input from generate out 0 and generate out 1 which is >>> maybe can be modeled is any output and pwm driver can register inputs >>> for pwm driver. >> >> I don't think that is a good model, since several bits (GENERATE, PWM, >> etc) need to be set in the TCSR, and we need to coordinate changes >> between timers closely to keep our contract for apply_state(). Although >> that is how the hardware is organized, the requirements of the >> clocksource and pwm subsystems are very different. > > There is another upstream solution done by samsung. Where they use > samsung,pwm-outputs property to identify PWMs. As I understand it, the samsung PWM/timer has 5 timers, four of which may be independently configured as PWMs. To contrast, this device has at most two timers, both of which must be used for a single PWM output. Because of this, it is sufficient to have a single property whose presence indicates that the device is to be configured as a PWM. > I think that make sense to consider to identify which timer should be > clocksource/clockevent because with MB SMP this has to be done to pair > timer with cpu for clockevents. This is not done by the current driver. The first timer in the system always binds itself to CPU 0. --Sean
diff --git a/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml new file mode 100644 index 000000000000..48a280f96e63 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/xlnx,axi-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx LogiCORE IP AXI Timer Device Tree Binding + +maintainers: + - Sean Anderson <sean.anderson@seco.com> + +properties: + compatible: + oneOf: + - items: + - const: xlnx,axi-timer-2.0 + - const: xlnx,xps-timer-1.00.a + - items: + - const: xlnx,xps-timer-1.00.a + + clocks: + maxItems: 1 + + clock-names: + const: s_axi_aclk + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + xlnx,count-width: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 8 + maximum: 32 + default: 32 + description: + The width of the counter(s), in bits. + + xlnx,one-timer-only: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + description: + Whether only one timer is present in this block. + +required: + - compatible + - reg + - xlnx,one-timer-only + +allOf: + - if: + required: + - '#pwm-cells' + then: + allOf: + - required: + - clocks + - properties: + xlnx,one-timer-only: + const: 0 + else: + required: + - interrupts + - if: + required: + - clocks + then: + required: + - clock-names + +additionalProperties: true + +examples: + - | + axi_timer_0: timer@800e0000 { + #pwm-cells = <0>; + clock-names = "s_axi_aclk"; + clocks = <&zynqmp_clk 71>; + compatible = "xlnx,axi-timer-2.0", "xlnx,xps-timer-1.00.a"; + reg = <0x800e0000 0x10000>; + xlnx,count-width = <0x20>; + xlnx,one-timer-only = <0x0>; + };
This adds a binding for the Xilinx LogiCORE IP AXI Timer. This device is a "soft" block, so it has many parameters which would not be configurable in most hardware. This binding is usually automatically generated by Xilinx's tools, so the names and values of some properties must be kept as they are. Replacement properties have been provided for new device trees. Because we need to init timer devices so early in boot, the easiest way to configure things is to use a device tree property. For the moment this is 'xlnx,pwm', but this could be extended/renamed/etc. in the future if these is a need for a generic property. Signed-off-by: Sean Anderson <sean.anderson@seco.com> --- Changes in v4: - Remove references to generate polarity so this can get merged - Predicate PWM driver on the presence of #pwm-cells - Make some properties optional for clocksource drivers Changes in v3: - Mark all boolean-as-int properties as deprecated - Add xlnx,pwm and xlnx,gen?-active-low properties. - Make newer replacement properties mutually-exclusive with what they replace - Add an example with non-deprecated properties only. Changes in v2: - Use 32-bit addresses for example binding .../bindings/pwm/xlnx,axi-timer.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/xlnx,axi-timer.yaml