Message ID | 20210511020500.17269-1-ansuelsmth@gmail.com |
---|---|
Headers | show |
Series | Multiple improvement to qca8k stability | expand |
On Tue, May 11, 2021 at 04:04:36AM +0200, Ansuel Smith wrote: > Change pr_err and pr_warn to dev variant. > > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> > Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew
> -static u32 > -qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val) > +static int > +qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val) > { > struct mii_bus *bus = priv->bus; > u16 r1, r2, page; > - u32 ret; > + u32 val; > + int ret; > > qca8k_split_addr(reg, &r1, &r2, &page); > > @@ -205,10 +206,15 @@ qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val) > if (ret < 0) > goto exit; > > - ret = qca8k_mii_read32(bus, 0x10 | r2, r1); > - ret &= ~mask; > - ret |= val; > - qca8k_mii_write32(bus, 0x10 | r2, r1, ret); > + val = qca8k_mii_read32(bus, 0x10 | r2, r1); > + if (val < 0) { > + ret = val; > + goto exit; > + } > + > + val &= ~mask; > + val |= write_val; > + qca8k_mii_write32(bus, 0x10 | r2, r1, val); Does qca8k_mii_write32() not return an code? Seems like yet another function you could modify. But i suggest you wait, get this patchset merged first. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew
On Tue, May 11, 2021 at 04:04:47AM +0200, Ansuel Smith wrote: > Limit port5 rx delay to qca8337. This is taken from the legacy QSDK code > that limits the rx delay on port5 to only this particular switch version, > on other switch only the tx and rx delay for port0 are needed. > > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> This should really be controlled by the phy-mode, but i suspect it is too late to fix now without breaking some boards. Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew
On Tue, May 11, 2021 at 04:04:51AM +0200, Ansuel Smith wrote: > The legacy qsdk code used a different delay instead of the max value. > Qsdk use 1 ms for rx and 2 ms for tx. Make these values configurable More likely to be ns not ms. > using the standard rx/tx-internal-delay-ps ethernet binding and apply > qsdk values by default. The connected gmac doesn't add any delay so no > additional delay is added to tx/rx. > On this switch the delay is actually in ms so value should be in the > 1000 order. Any value converted from ps to ms by deviding it by 1000 > as the switch max value for delay is 3ms. dividing. And more ms that should be ns. Andrew
On Tue, May 11, 2021 at 04:04:53AM +0200, Ansuel Smith wrote: > MDIO_MASTER operation have a dedicated busy wait that is not protected > by the mdio mutex. This can cause situation where the MASTER operation > is done and a normal operation is executed between the MASTER read/write > and the MASTER busy_wait. Rework the qca8k_mdio_read/write function to > address this issue by binding the lock for the whole MASTER operation > and not only the mdio read/write common operation. > > Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew