mbox series

[v7,0/8] Couple improvements for Tegra clk driver

Message ID 20210510231737.30313-1-digetx@gmail.com
Headers show
Series Couple improvements for Tegra clk driver | expand

Message

Dmitry Osipenko May 10, 2021, 11:17 p.m. UTC 
This series fixes couple minor standalone problems of the Tegra clk
driver and adds new features.

Changelog:

v7: - Added r-b from Rob Herring to the schema patch which he gave to v6.

    - Dropped the MAINTAINERS-update patch. Previously Peter said on IRC
      that he doesn't have time on the tegra-clk driver anymore and approved
      the patch, but then he refused to ack the v6 patch, saying that he
      is not reading mailing lists. So I don't feel comfortable with that
      patch. Peter could send it by himself if will be necessary.

    - Added these new patches:

        clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling
        clk: tegra: Mark external clocks as not having reset control

      I sent out the new Tegra30 thermal sensor driver and now CPU clock
      could be throttled by the sensor hardware [1]. The first patch adds
      support for reporting of the throttled frequency properly.

      [1] https://patchwork.ozlabs.org/project/linux-tegra/list/?series=243126

      During of debugging sound issues of Asus Transformer devices, I noticed
      that the external clocks are missing the no-reset flag. The second
      patch fixes it.

v6: - Made a small improvement and corrected a typo in patch
      "Fix refcounting of gate clocks" that were spotted by
      Michał Mirosław.

v5: - Corrected example in the schema binding to silence dt_binding_check
      warning.

    - The Tegra124 binding is factored out into standalone binding since
      Tegra124 has properties that aren't used by other SoCs and I couldn't
      figure out how to make them conditional in schema.

v4: - Added new patch that converts DT bindings to schema.

v3: - Added acks from Thierry Reding that he gave to v2.

    - Added new patch "clk: tegra: Don't allow zero clock rate for PLLs".

v2: - Added these new patches:

      clk: tegra: Halve SCLK rate on Tegra20
      MAINTAINERS: Hand Tegra clk driver to Jon and Thierry

v1: - Collected clk patches into a single series.

Dmitry Osipenko (8):
  clk: tegra30: Use 300MHz for video decoder by default
  clk: tegra: Fix refcounting of gate clocks
  clk: tegra: Ensure that PLLU configuration is applied properly
  clk: tegra: Halve SCLK rate on Tegra20
  clk: tegra: Don't allow zero clock rate for PLLs
  clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling
  clk: tegra: Mark external clocks as not having reset control
  dt-bindings: clock: tegra: Convert to schema

 .../bindings/clock/nvidia,tegra114-car.txt    |  63 ----------
 .../bindings/clock/nvidia,tegra124-car.txt    | 107 ----------------
 .../bindings/clock/nvidia,tegra124-car.yaml   | 115 ++++++++++++++++++
 .../bindings/clock/nvidia,tegra20-car.txt     |  63 ----------
 .../bindings/clock/nvidia,tegra20-car.yaml    |  69 +++++++++++
 .../bindings/clock/nvidia,tegra210-car.txt    |  56 ---------
 .../bindings/clock/nvidia,tegra30-car.txt     |  63 ----------
 drivers/clk/tegra/clk-periph-gate.c           |  72 +++++++----
 drivers/clk/tegra/clk-periph.c                |  11 ++
 drivers/clk/tegra/clk-pll.c                   |  12 +-
 drivers/clk/tegra/clk-tegra-periph.c          |   6 +-
 drivers/clk/tegra/clk-tegra-super-cclk.c      |  16 ++-
 drivers/clk/tegra/clk-tegra20.c               |   6 +-
 drivers/clk/tegra/clk-tegra30.c               |   4 +-
 14 files changed, 271 insertions(+), 392 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
 delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-car.txt
 create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-car.yaml
 delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
 create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra20-car.yaml
 delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra210-car.txt
 delete mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra30-car.txt

Comments

Michał Mirosław May 11, 2021, 2:41 p.m. UTC | #1 
On Tue, May 11, 2021 at 02:17:35AM +0300, Dmitry Osipenko wrote:
> Check whether thermal DIV2 throttle is active in order to report
> the CPU frequency properly. This very useful for userspace tools
> like cpufreq-info which show actual frequency asserted from hardware.
> 
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
>  drivers/clk/tegra/clk-tegra-super-cclk.c | 16 ++++++++++++++--
>  drivers/clk/tegra/clk-tegra30.c          |  2 +-
>  2 files changed, 15 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c
> index a03119c30456..f75822b71d0e 100644
> --- a/drivers/clk/tegra/clk-tegra-super-cclk.c
> +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c
> @@ -25,6 +25,8 @@
>  
>  #define SUPER_CDIV_ENB		BIT(31)
>  
> +#define TSENSOR_SLOWDOWN	BIT(23)
> +
>  static struct tegra_clk_super_mux *cclk_super;
>  static bool cclk_on_pllx;
>  
> @@ -47,10 +49,20 @@ static int cclk_super_set_rate(struct clk_hw *hw, unsigned long rate,
>  static unsigned long cclk_super_recalc_rate(struct clk_hw *hw,
>  					    unsigned long parent_rate)
>  {
> +	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
> +	u32 val = readl_relaxed(super->reg);
> +	unsigned int div2;
> +
> +	/* check whether thermal throttling is active */
> +	if (val & TSENSOR_SLOWDOWN)
> +		div2 = 2;
> +	else
> +		div2 = 1;
> +
>  	if (cclk_super_get_parent(hw) == PLLX_INDEX)
> -		return parent_rate;
> +		return parent_rate / div2;
>  
> -	return tegra_clk_super_ops.recalc_rate(hw, parent_rate);
> +	return tegra_clk_super_ops.recalc_rate(hw, parent_rate) / div2;
>  }

Could you check if the compiler can optimize out the division? I know this
is a slow path, but nevertheless the 'shr' version would be the same amount
of source code.

Best Regrads
Michał Mirosław
Dmitry Osipenko May 11, 2021, 3:23 p.m. UTC | #2 
11.05.2021 17:41, Michał Mirosław пишет:
> On Tue, May 11, 2021 at 02:17:35AM +0300, Dmitry Osipenko wrote:
>> Check whether thermal DIV2 throttle is active in order to report
>> the CPU frequency properly. This very useful for userspace tools
>> like cpufreq-info which show actual frequency asserted from hardware.
>>
>> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
>> ---
>>  drivers/clk/tegra/clk-tegra-super-cclk.c | 16 ++++++++++++++--
>>  drivers/clk/tegra/clk-tegra30.c          |  2 +-
>>  2 files changed, 15 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/clk/tegra/clk-tegra-super-cclk.c b/drivers/clk/tegra/clk-tegra-super-cclk.c
>> index a03119c30456..f75822b71d0e 100644
>> --- a/drivers/clk/tegra/clk-tegra-super-cclk.c
>> +++ b/drivers/clk/tegra/clk-tegra-super-cclk.c
>> @@ -25,6 +25,8 @@
>>  
>>  #define SUPER_CDIV_ENB		BIT(31)
>>  
>> +#define TSENSOR_SLOWDOWN	BIT(23)
>> +
>>  static struct tegra_clk_super_mux *cclk_super;
>>  static bool cclk_on_pllx;
>>  
>> @@ -47,10 +49,20 @@ static int cclk_super_set_rate(struct clk_hw *hw, unsigned long rate,
>>  static unsigned long cclk_super_recalc_rate(struct clk_hw *hw,
>>  					    unsigned long parent_rate)
>>  {
>> +	struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
>> +	u32 val = readl_relaxed(super->reg);
>> +	unsigned int div2;
>> +
>> +	/* check whether thermal throttling is active */
>> +	if (val & TSENSOR_SLOWDOWN)
>> +		div2 = 2;
>> +	else
>> +		div2 = 1;
>> +
>>  	if (cclk_super_get_parent(hw) == PLLX_INDEX)
>> -		return parent_rate;
>> +		return parent_rate / div2;
>>  
>> -	return tegra_clk_super_ops.recalc_rate(hw, parent_rate);
>> +	return tegra_clk_super_ops.recalc_rate(hw, parent_rate) / div2;
>>  }
> 
> Could you check if the compiler can optimize out the division? I know this
> is a slow path, but nevertheless the 'shr' version would be the same amount
> of source code.

Hello Michał,

GCC can't optimize that division. I'll wait for more comments and then
update this patch in v8 with yours suggestion. Thank you for taking a
look at the patches.