| Message ID | FITkUaiC5DeyCU3e1T6EisgkkQ8Fnrwf2WZTBGE@cp4-web-031.plabs.ch |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] This makes it easier to figure out whether a particular instruction was actually translated. | expand |
On 5/7/21 3:48 PM, Nathan Ringo wrote: > - trace_translate_block(tb, tb->pc, tb->tc.ptr); > + trace_translate_block(tb, tb->pc, (int)tb->icount, tb->tc.ptr); What target are you looking at, because for the variable-length isa's, instruction count may not really help. Perhaps tb->size instead? r~
I'm mostly looking at AArch64, so they're the same there :) I'm using this to collect code coverage information, so I have the disassembly, and it's slightly easier to report it that way; if you think it'd be more useful on other architectures to report the byte range instead, it'd be an easy change to my scripts. Also, noticed I accidentally deleted the first line of the commit message when I updated the patch... I can fix that if you want me to switch the size metric.
Nathan Ringo <nathan@remexre.xyz> writes: > I'm mostly looking at AArch64, so they're the same there :) I'm using > this to collect code coverage information, so I have the disassembly, > and it's slightly easier to report it that way; Have you considered collecting this information with TCG plugins? That way you can instrument what was actually instrumented directly. > if you think it'd be > more useful on other architectures to report the byte range instead, > it'd be an easy change to my scripts. > > Also, noticed I accidentally deleted the first line of the commit > message when I updated the patch... I can fix that if you want me to > switch the size metric.
diff --git a/accel/tcg/trace-events b/accel/tcg/trace-events index 6eefb37f5d..c227e56248 100644 --- a/accel/tcg/trace-events +++ b/accel/tcg/trace-events @@ -7,4 +7,4 @@ exec_tb_nocache(void *tb, uintptr_t pc) "tb:%p pc=0x%"PRIxPTR exec_tb_exit(void *last_tb, unsigned int flags) "tb:%p flags=0x%x" # translate-all.c -translate_block(void *tb, uintptr_t pc, const void *tb_code) "tb:%p, pc:0x%"PRIxPTR", tb_code:%p" +translate_block(void *tb, uintptr_t pc, int num_insns, const void *tb_code) "tb:%p, pc:0x%"PRIxPTR", num_insns:%d, tb_code:%p" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index b12d0898d0..2c70eec777 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1916,7 +1916,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->cpu = NULL; max_insns = tb->icount; - trace_translate_block(tb, tb->pc, tb->tc.ptr); + trace_translate_block(tb, tb->pc, (int)tb->icount, tb->tc.ptr); /* generate machine code */ tb->jmp_reset_offset[0] = TB_JMP_RESET_OFFSET_INVALID;
Signed-off-by: Nathan Ringo <nathan@remexre.xyz> --- accel/tcg/trace-events | 2 +- accel/tcg/translate-all.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-)