diff mbox series

[6/8] mtd: rawnand: jz4780-bch: Don't set clock rate in driver

Message ID 20190118010634.27399-6-paul@crapouillou.net
State Changes Requested
Delegated to: Miquel Raynal
Headers show
Series [1/8] MIPS: DTS: CI20: Set BCH clock to 200 MHz | expand

Commit Message

Paul Cercueil Jan. 18, 2019, 1:06 a.m. UTC
This should be done in devicetree. Besides, it prevents us from
supporting other SoCs which don't use the same clock frequency for the
BCH hardware.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
 drivers/mtd/nand/raw/jz4780_bch.c | 4 ----
 1 file changed, 4 deletions(-)

Comments

Boris Brezillon Jan. 18, 2019, 8:31 a.m. UTC | #1
On Thu, 17 Jan 2019 22:06:32 -0300
Paul Cercueil <paul@crapouillou.net> wrote:

> This should be done in devicetree. Besides, it prevents us from
> supporting other SoCs which don't use the same clock frequency for the
> BCH hardware.

As I said earlier, I disagree with this statement, plus, you're
breaking backward compat with existing DTs when doing that.

> 
> Signed-off-by: Paul Cercueil <paul@crapouillou.net>
> ---
>  drivers/mtd/nand/raw/jz4780_bch.c | 4 ----
>  1 file changed, 4 deletions(-)
> 
> diff --git a/drivers/mtd/nand/raw/jz4780_bch.c b/drivers/mtd/nand/raw/jz4780_bch.c
> index 7e4e5e627603..161d3821e1c4 100644
> --- a/drivers/mtd/nand/raw/jz4780_bch.c
> +++ b/drivers/mtd/nand/raw/jz4780_bch.c
> @@ -57,8 +57,6 @@
>  #define BCH_BHINT_UNCOR			BIT(1)
>  #define BCH_BHINT_ERR			BIT(0)
>  
> -#define BCH_CLK_RATE			(200 * 1000 * 1000)
> -
>  /* Timeout for BCH calculation/correction. */
>  #define BCH_TIMEOUT_US			100000
>  
> @@ -348,8 +346,6 @@ static int jz4780_bch_probe(struct platform_device *pdev)
>  		return PTR_ERR(bch->clk);
>  	}
>  
> -	clk_set_rate(bch->clk, BCH_CLK_RATE);
> -
>  	mutex_init(&bch->lock);
>  
>  	bch->dev = dev;
diff mbox series

Patch

diff --git a/drivers/mtd/nand/raw/jz4780_bch.c b/drivers/mtd/nand/raw/jz4780_bch.c
index 7e4e5e627603..161d3821e1c4 100644
--- a/drivers/mtd/nand/raw/jz4780_bch.c
+++ b/drivers/mtd/nand/raw/jz4780_bch.c
@@ -57,8 +57,6 @@ 
 #define BCH_BHINT_UNCOR			BIT(1)
 #define BCH_BHINT_ERR			BIT(0)
 
-#define BCH_CLK_RATE			(200 * 1000 * 1000)
-
 /* Timeout for BCH calculation/correction. */
 #define BCH_TIMEOUT_US			100000
 
@@ -348,8 +346,6 @@  static int jz4780_bch_probe(struct platform_device *pdev)
 		return PTR_ERR(bch->clk);
 	}
 
-	clk_set_rate(bch->clk, BCH_CLK_RATE);
-
 	mutex_init(&bch->lock);
 
 	bch->dev = dev;