| Message ID | CY1PR12MB00420E90B52B0F478D9DF1CDDCE30@CY1PR12MB0042.namprd12.prod.outlook.com |
|---|---|
| State | New |
| Headers | show |
On Wed, Aug 31, 2016 at 10:50 AM, Agrawal, Nitesh-kumar <Nitesh-kumar.Agrawal@amd.com> wrote: I'm adding Wei and Wang to the patch as they worked on the driver in the past and I'd like to hear what they say. Could you folks provide some ACK or comments? The indentation is horrible in the patch, I don't know if it is a result of the mailer though, the it's not your fault and I can fix it up for sure if you have a problem getting it right. Just make sure you run scripts/checkpatch.pl before sending the patches. > In the function amd_gpio_irq_set_type, use the settings provided by > the BIOS,when the LevelTrig is Edge and activeLevel is HIGH, to configure > the GPIO registers. Ignore the settings from client. > > Reviewed-by:Pankaj Sen <Pankaj.Sen@amd.com> > Signed-off-by:Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com> > --- > drivers/pinctrl/pinctrl-amd.c | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c > index 828148d..a645082 100644 > --- a/drivers/pinctrl/pinctrl-amd.c > +++ b/drivers/pinctrl/pinctrl-amd.c > @@ -385,12 +385,26 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) > int ret = 0; > u32 pin_reg; > unsigned long flags; > + u32 levelTrig; Please refrain from using CamelCase, just call it level_trig. Also: this seems to be a bool. > + u32 activeLevel; No CamelCase. This doesn't seem to be a bool though, can't really tell. > struct gpio_chip *gc = irq_data_get_irq_chip_data(d); > struct amd_gpio *gpio_dev = gpiochip_get_data(gc); > > spin_lock_irqsave(&gpio_dev->lock, flags); > pin_reg = readl(gpio_dev->base + (d->hwirq)*4); > > + /* > + When LevelTrig is set EDGE and activeLevel is set HIGH in BIOS > + default settings, ignore incoming settings from client and use > + BIOS settings to configure GPIO register. > + */ /* * Please comment like this * with a star in the beginning on every line * I know I am picky. */ > + levelTrig = pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF); So if this was a bool it would be: level_trig = !!(pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF)); Notice how the double-bang (!!) clamps the result to a bool. > + activeLevel = pin_reg & (ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); > + > + if((!levelTrig)&&((activeLevel>> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH)) { > + type = IRQ_TYPE_EDGE_FALLING; > + } The thing looks a bit unorthodox but I guess you know what you're doing. Yours, Linus Walleij -- To unsubscribe from this list: send the line "unsubscribe linux-gpio" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 828148d..a645082 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -385,12 +385,26 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) int ret = 0; u32 pin_reg; unsigned long flags; + u32 levelTrig; + u32 activeLevel; struct gpio_chip *gc = irq_data_get_irq_chip_data(d); struct amd_gpio *gpio_dev = gpiochip_get_data(gc); spin_lock_irqsave(&gpio_dev->lock, flags); pin_reg = readl(gpio_dev->base + (d->hwirq)*4); + /* + When LevelTrig is set EDGE and activeLevel is set HIGH in BIOS + default settings, ignore incoming settings from client and use + BIOS settings to configure GPIO register. + */ + levelTrig = pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF); + activeLevel = pin_reg & (ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); + + if((!levelTrig)&&((activeLevel>> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH)) { + type = IRQ_TYPE_EDGE_FALLING; + } + switch (type & IRQ_TYPE_SENSE_MASK) { case IRQ_TYPE_EDGE_RISING: pin_reg &= ~BIT(LEVEL_TRIG_OFF);