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GET /api/patches/2185055/?format=api
{ "id": 2185055, "url": "http://patchwork.ozlabs.org/api/patches/2185055/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/patch/20260116074425.1208705-2-xiejiamei@hygon.cn/", "project": { "id": 41, "url": "http://patchwork.ozlabs.org/api/projects/41/?format=api", "name": "GNU C Library", "link_name": "glibc", "list_id": "libc-alpha.sourceware.org", "list_email": "libc-alpha@sourceware.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260116074425.1208705-2-xiejiamei@hygon.cn>", "list_archive_url": null, "date": "2026-01-16T07:44:25", "name": "[v2,1/1] x86: Fix for cache computation on Hygon under hypervisors", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "68b74646ce3033fbc91a3c2317f50bfacfcaa4a4", "submitter": { "id": 91872, "url": "http://patchwork.ozlabs.org/api/people/91872/?format=api", "name": "Jiamei Xie", "email": "xiejiamei@hygon.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/glibc/patch/20260116074425.1208705-2-xiejiamei@hygon.cn/mbox/", "series": [ { "id": 488578, "url": "http://patchwork.ozlabs.org/api/series/488578/?format=api", "web_url": "http://patchwork.ozlabs.org/project/glibc/list/?series=488578", "date": "2026-01-16T07:44:24", "name": "x86: Fix for cache computation on Hygon", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/488578/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2185055/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2185055/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "libc-alpha@sourceware.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "libc-alpha@sourceware.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=sourceware.org\n (client-ip=2620:52:6:3111::32; helo=vm01.sourceware.org;\n envelope-from=libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org;\n dmarc=pass (p=none dis=none) header.from=hygon.cn", "sourceware.org; spf=pass smtp.mailfrom=hygon.cn", "server2.sourceware.org;\n arc=none smtp.remote-ip=101.204.27.37" ], "Received": [ "from vm01.sourceware.org (vm01.sourceware.org\n [IPv6:2620:52:6:3111::32])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4dssNp4Cf6z1xsy\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 16 Jan 2026 18:46:18 +1100 (AEDT)", "from vm01.sourceware.org (localhost [127.0.0.1])\n\tby sourceware.org (Postfix) with ESMTP id 6FB0E4BA2E2F\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 16 Jan 2026 07:46:16 +0000 (GMT)", "from mailgw2.hygon.cn (unknown [101.204.27.37])\n by sourceware.org (Postfix) with ESMTP id 482284BA2E1D\n for <libc-alpha@sourceware.org>; Fri, 16 Jan 2026 07:45:26 +0000 (GMT)", "from maildlp2.hygon.cn (unknown [127.0.0.1])\n by mailgw2.hygon.cn (Postfix) with ESMTP id 4dssMm3HHnz1YFqxm\n for <libc-alpha@sourceware.org>; Fri, 16 Jan 2026 15:45:24 +0800 (CST)", "from maildlp2.hygon.cn (unknown [172.23.18.61])\n by mailgw2.hygon.cn (Postfix) with ESMTP id 4dssMl6gfRz1YFqxm\n for <libc-alpha@sourceware.org>; Fri, 16 Jan 2026 15:45:23 +0800 (CST)", "from cncheex04.Hygon.cn (unknown [172.23.18.114])\n by maildlp2.hygon.cn (Postfix) with ESMTPS id 3F4F730004D0\n for <libc-alpha@sourceware.org>; Fri, 16 Jan 2026 15:45:14 +0800 (CST)", "from jianyong.hygon.cn (172.19.20.52) by cncheex04.Hygon.cn\n (172.23.18.114) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.36; Fri, 16 Jan\n 2026 15:45:23 +0800" ], "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 sourceware.org 6FB0E4BA2E2F", "OpenDKIM Filter v2.11.0 sourceware.org 482284BA2E1D" ], "DMARC-Filter": "OpenDMARC Filter v1.4.2 sourceware.org 482284BA2E1D", "ARC-Filter": "OpenARC Filter v1.0.0 sourceware.org 482284BA2E1D", "ARC-Seal": "i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1768549527; cv=none;\n b=Z4g+Pa0GipV7lNMQvazbd4vo+qqQnRaaWJGFxUmfYPM+MbHBQTo9NdXOVWIor1b1U+j6AodTCZFlyuYC6VPCPNrIhBgqtvm+TEPl4j/H73rH3dUv1aNIy4tFM8W4tYk6NJzxxciDOID/WTlFktZPYgFdDXrWEftoV2YsuOg3A6g=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=sourceware.org; s=key;\n t=1768549527; c=relaxed/simple;\n bh=l5iqJllkel9RxTUgDLeT6cyv3IYkk/T+0Oe1GgzYR30=;\n h=From:To:Subject:Date:Message-ID:MIME-Version;\n b=OJVx1UN1cnDa25ikoEdGlP89SkcnYOOv1MIo4hM+lJF4F0ECzbcdnqpTSuLNN2m+I+lG+iTf3c1tSXiXj3M9DthktUIUipJOFqEEF+2rBx1+/91rHmaIUUik5a/I5qBqR2/a1aAKgT8/u0kgSxSVYS3Bi7CXIeww5CkERdHxtzI=", "ARC-Authentication-Results": "i=1; server2.sourceware.org", "From": "Jiamei Xie <xiejiamei@hygon.cn>", "To": "<libc-alpha@sourceware.org>", "CC": "<lijing@hygon.cn>, Jiamei Xie <xiejiamei@hygon.cn>", "Subject": "[PATCH v2 1/1] x86: Fix for cache computation on Hygon under\n hypervisors", "Date": "Fri, 16 Jan 2026 15:44:25 +0800", "Message-ID": "<20260116074425.1208705-2-xiejiamei@hygon.cn>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260116074425.1208705-1-xiejiamei@hygon.cn>", "References": "<20260116074425.1208705-1-xiejiamei@hygon.cn>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.19.20.52]", "X-ClientProxiedBy": "cncheex05.Hygon.cn (172.23.18.115) To cncheex04.Hygon.cn\n (172.23.18.114)", "X-BeenThere": "libc-alpha@sourceware.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Libc-alpha mailing list <libc-alpha.sourceware.org>", "List-Unsubscribe": "<https://sourceware.org/mailman/options/libc-alpha>,\n <mailto:libc-alpha-request@sourceware.org?subject=unsubscribe>", "List-Archive": "<https://sourceware.org/pipermail/libc-alpha/>", "List-Post": "<mailto:libc-alpha@sourceware.org>", "List-Help": "<mailto:libc-alpha-request@sourceware.org?subject=help>", "List-Subscribe": "<https://sourceware.org/mailman/listinfo/libc-alpha>,\n <mailto:libc-alpha-request@sourceware.org?subject=subscribe>", "Errors-To": "libc-alpha-bounces~incoming=patchwork.ozlabs.org@sourceware.org" }, "content": "On Hygon CPUs, glibc currently relies on CPUID leaf 0x8000001D to\ncompute cache parameters. This works correctly on bare-metal\nsystems. However, under some hypervisors (e.g. QEMU with -cpu\nqemu64), the maximum supported extended CPUID leaf is only\n0x8000000A, and CPUID 0x8000001D is not exposed. In this case,\ncache information computed via 0x8000001D is zeroed out.\n\nThis patch introduces legacy fallback of cache computation based on\nCPUID 0x80000005 and 0x80000006, consistent with the AMD\nimplementation, to restore correct cache information under such\nenvironments.\n\nSigned-off-by: Jiamei Xie <xiejiamei@hygon.cn>\n---\n sysdeps/x86/dl-cacheinfo.h | 201 +++++++++++++++++++++++++++++++++----\n 1 file changed, 179 insertions(+), 22 deletions(-)", "diff": "diff --git a/sysdeps/x86/dl-cacheinfo.h b/sysdeps/x86/dl-cacheinfo.h\nindex b6520bddaa..d2d4301bc7 100644\n--- a/sysdeps/x86/dl-cacheinfo.h\n+++ b/sysdeps/x86/dl-cacheinfo.h\n@@ -585,35 +585,192 @@ handle_hygon (int name)\n unsigned int ebx;\n unsigned int ecx;\n unsigned int edx;\n- unsigned int count = 0x1;\n+ unsigned int max_cpuid = 0;\n+\n+ /* No level 4 cache (yet). */\n+ if (name > _SC_LEVEL3_CACHE_LINESIZE)\n+ return 0;\n+\n+ __cpuid (0x80000000, max_cpuid, ebx, ecx, edx);\n+\n+ if (max_cpuid >= 0x8000001D)\n+ /* Use __cpuid__ '0x8000_001D' to compute cache details. */\n+ {\n+ unsigned int count = 0x1;\n \n- if (name >= _SC_LEVEL3_CACHE_SIZE)\n- count = 0x3;\n- else if (name >= _SC_LEVEL2_CACHE_SIZE)\n- count = 0x2;\n- else if (name >= _SC_LEVEL1_DCACHE_SIZE)\n- count = 0x0;\n+ if (name >= _SC_LEVEL3_CACHE_SIZE)\n+ count = 0x3;\n+ else if (name >= _SC_LEVEL2_CACHE_SIZE)\n+ count = 0x2;\n+ else if (name >= _SC_LEVEL1_DCACHE_SIZE)\n+ count = 0x0;\n+\n+ __cpuid_count (0x8000001D, count, eax, ebx, ecx, edx);\n \n- /* Use __cpuid__ '0x8000_001D' to compute cache details. */\n- __cpuid_count (0x8000001D, count, eax, ebx, ecx, edx);\n+ if (ecx != 0)\n+ {\n+ switch (name)\n+ {\n+ case _SC_LEVEL1_ICACHE_ASSOC:\n+ case _SC_LEVEL1_DCACHE_ASSOC:\n+ case _SC_LEVEL2_CACHE_ASSOC:\n+ case _SC_LEVEL3_CACHE_ASSOC:\n+ return ((ebx >> 22) & 0x3ff) + 1;\n+ case _SC_LEVEL1_ICACHE_LINESIZE:\n+ case _SC_LEVEL1_DCACHE_LINESIZE:\n+ case _SC_LEVEL2_CACHE_LINESIZE:\n+ case _SC_LEVEL3_CACHE_LINESIZE:\n+ return (ebx & 0xfff) + 1;\n+ case _SC_LEVEL1_ICACHE_SIZE:\n+ case _SC_LEVEL1_DCACHE_SIZE:\n+ case _SC_LEVEL2_CACHE_SIZE:\n+ case _SC_LEVEL3_CACHE_SIZE:\n+ return (((ebx >> 22) & 0x3ff) + 1) * ((ebx & 0xfff) + 1) * (ecx + 1);\n+ default:\n+ __builtin_unreachable ();\n+ }\n+ return -1;\n+ }\n+ }\n+\n+ /* Legacy cache computation for some hypervisors that\n+ accidentally configure __cpuid__ '0x8000_001D' to Zero. */\n+\n+ unsigned int fn = 0x80000005 + (name >= _SC_LEVEL2_CACHE_SIZE);\n+\n+ if (max_cpuid < fn)\n+ return 0;\n+\n+ __cpuid (fn, eax, ebx, ecx, edx);\n+\n+ if (name < _SC_LEVEL1_DCACHE_SIZE)\n+ {\n+ name += _SC_LEVEL1_DCACHE_SIZE - _SC_LEVEL1_ICACHE_SIZE;\n+ ecx = edx;\n+ }\n \n switch (name)\n {\n- case _SC_LEVEL1_ICACHE_ASSOC:\n- case _SC_LEVEL1_DCACHE_ASSOC:\n- case _SC_LEVEL2_CACHE_ASSOC:\n+ case _SC_LEVEL1_DCACHE_SIZE:\n+ return (ecx >> 14) & 0x3fc00;\n+\n+ case _SC_LEVEL1_DCACHE_ASSOC:\n+ ecx >>= 16;\n+ if ((ecx & 0xff) == 0xff)\n+ {\n+ /* Fully associative. */\n+ return (ecx << 2) & 0x3fc00;\n+ }\n+ return ecx & 0xff;\n+\n+ case _SC_LEVEL1_DCACHE_LINESIZE:\n+ return ecx & 0xff;\n+\n+ case _SC_LEVEL2_CACHE_SIZE:\n+ return (ecx & 0xf000) == 0 ? 0 : (ecx >> 6) & 0x3fffc00;\n+\n+ case _SC_LEVEL2_CACHE_ASSOC:\n+ switch ((ecx >> 12) & 0xf)\n+ {\n+ case 0:\n+ case 1:\n+ case 2:\n+ case 4:\n+ return (ecx >> 12) & 0xf;\n+ case 6:\n+ return 8;\n+ case 8:\n+ return 16;\n+ case 10:\n+ return 32;\n+ case 11:\n+ return 48;\n+ case 12:\n+ return 64;\n+ case 13:\n+ return 96;\n+ case 14:\n+ return 128;\n+ case 15:\n+ return ((ecx >> 6) & 0x3fffc00) / (ecx & 0xff);\n+ default:\n+ return 0;\n+ }\n+\n+ case _SC_LEVEL2_CACHE_LINESIZE:\n+ return (ecx & 0xf000) == 0 ? 0 : ecx & 0xff;\n+\n+ case _SC_LEVEL3_CACHE_SIZE:\n+ {\n+ long int total_l3_cache = 0, l3_cache_per_thread = 0;\n+ unsigned int threads = 0;\n+\n+ if ((edx & 0xf000) == 0)\n+ return 0;\n+\n+ total_l3_cache = (edx & 0x3ffc0000) << 1;\n+\n+ /* Figure out the number of logical threads that share L3. */\n+ if (max_cpuid >= 0x80000008)\n+ {\n+ /* Get width of APIC ID. */\n+ __cpuid (0x80000008, eax, ebx, ecx, edx);\n+ threads = (ecx & 0xff) + 1;\n+ }\n+\n+ if (threads == 0)\n+ {\n+ /* If APIC ID width is not available, use logical\n+ processor count. */\n+ __cpuid (0x00000001, eax, ebx, ecx, edx);\n+ if ((edx & (1 << 28)) != 0)\n+ threads = (ebx >> 16) & 0xff;\n+ }\n+\n+ /* Cap usage of highest cache level to the number of\n+ supported threads. */\n+ if (threads > 0)\n+ l3_cache_per_thread = total_l3_cache/threads;\n+\n+ /* Get shared cache per ccx. */\n+ /* Get number of threads share the L3 cache in CCX. */\n+ __cpuid_count (0x8000001D, 0x3, eax, ebx, ecx, edx);\n+ unsigned int threads_per_ccx = ((eax >> 14) & 0xfff) + 1;\n+ long int l3_cache_per_ccx = l3_cache_per_thread * threads_per_ccx;\n+ return l3_cache_per_ccx;\n+ }\n+\n case _SC_LEVEL3_CACHE_ASSOC:\n- return ((ebx >> 22) & 0x3ff) + 1;\n- case _SC_LEVEL1_ICACHE_LINESIZE:\n- case _SC_LEVEL1_DCACHE_LINESIZE:\n- case _SC_LEVEL2_CACHE_LINESIZE:\n+ switch ((edx >> 12) & 0xf)\n+ {\n+ case 0:\n+ case 1:\n+ case 2:\n+ case 4:\n+ return (edx >> 12) & 0xf;\n+ case 6:\n+ return 8;\n+ case 8:\n+ return 16;\n+ case 10:\n+ return 32;\n+ case 11:\n+ return 48;\n+ case 12:\n+ return 64;\n+ case 13:\n+ return 96;\n+ case 14:\n+ return 128;\n+ case 15:\n+ return ((edx & 0x3ffc0000) << 1) / (edx & 0xff);\n+ default:\n+ return 0;\n+ }\n+\n case _SC_LEVEL3_CACHE_LINESIZE:\n- return (ebx & 0xfff) + 1;\n- case _SC_LEVEL1_ICACHE_SIZE:\n- case _SC_LEVEL1_DCACHE_SIZE:\n- case _SC_LEVEL2_CACHE_SIZE:\n- case _SC_LEVEL3_CACHE_SIZE:\n- return (((ebx >> 22) & 0x3ff) + 1) * ((ebx & 0xfff) + 1) * (ecx + 1);\n+ return (edx & 0xf000) == 0 ? 0 : edx & 0xff;\n+\n default:\n __builtin_unreachable ();\n }\n", "prefixes": [ "v2", "1/1" ] }