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GET /api/patches/1886150/?format=api
{ "id": 1886150, "url": "http://patchwork.ozlabs.org/api/patches/1886150/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20240112142621.13525-4-prabhakar.mahadev-lad.rj@bp.renesas.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20240112142621.13525-4-prabhakar.mahadev-lad.rj@bp.renesas.com>", "list_archive_url": null, "date": "2024-01-12T14:26:20", "name": "[v4,3/4] pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "16ae4e710a4e8d92339999c24937527319e632cd", "submitter": { "id": 9539, "url": "http://patchwork.ozlabs.org/api/people/9539/?format=api", "name": "Lad, Prabhakar", "email": "prabhakar.csengg@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20240112142621.13525-4-prabhakar.mahadev-lad.rj@bp.renesas.com/mbox/", "series": [ { "id": 390295, "url": "http://patchwork.ozlabs.org/api/series/390295/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=390295", "date": "2024-01-12T14:26:17", "name": "Add missing port pins for RZ/Five SoC", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/390295/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1886150/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1886150/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-2168-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20230601 header.b=aonVm94Q;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2604:1380:45d1:ec00::1; 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These additional\npins provide expanded capabilities and are exclusive to the RZ/Five SoC.\n\nCouple of port pins have different configuration and are not identical for\nthe complete port so introduce struct rzg2l_variable_pin_cfg to handle\nsuch cases and introduce the PIN_CFG_VARIABLE macro. The actual pin config\nis then assigned in rzg2l_pinctrl_get_variable_pin_cfg().\n\nAdd an additional check in rzg2l_gpio_get_gpioint() to only allow GPIO pins\nwhich support interrupt facility.\n\nWhile at define RZG2L_GPIO_PORT_PACK() using RZG2L_GPIO_PORT_SPARSE_PACK().\n\nSigned-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>\n---\n drivers/pinctrl/renesas/pinctrl-rzg2l.c | 213 +++++++++++++++++++++++-\n 1 file changed, 204 insertions(+), 9 deletions(-)", "diff": "diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\nindex 8b8644d2c355..04bb21d564d4 100644\n--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c\n@@ -57,6 +57,8 @@\n #define PIN_CFG_IOLH_C\t\t\tBIT(13)\n #define PIN_CFG_SOFT_PS\t\t\tBIT(14)\n #define PIN_CFG_OEN\t\t\tBIT(15)\n+#define PIN_CFG_VARIABLE\t\tBIT(16)\n+#define PIN_CFG_NOGPIO_INT\t\tBIT(17)\n \n #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \\\n \t\t\t\t\t(PIN_CFG_IOLH_##group | \\\n@@ -76,17 +78,23 @@\n \t\t\t\t\t PIN_CFG_FILNUM | \\\n \t\t\t\t\t PIN_CFG_FILCLKSEL)\n \n-/*\n- * n indicates number of pins in the port, a is the register index\n- * and f is pin configuration capabilities supported.\n- */\n #define PIN_CFG_PIN_MAP_MASK\t\tGENMASK(35, 28)\n #define PIN_CFG_PIN_REG_MASK\t\tGENMASK(27, 20)\n #define PIN_CFG_MASK\t\t\tGENMASK(19, 0)\n \n-#define RZG2L_GPIO_PORT_PACK(n, a, f)\t((((1ULL << (n)) - 1) << 28) | \\\n-\t\t\t\t\t FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \\\n-\t\t\t\t\t FIELD_PREP_CONST(PIN_CFG_MASK, (f)))\n+/*\n+ * m indicates the bitmap of supported pins, a is the register index\n+ * and f is pin configuration capabilities supported.\n+ */\n+#define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f)\t(FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \\\n+\t\t\t\t\t\t FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \\\n+\t\t\t\t\t\t FIELD_PREP_CONST(PIN_CFG_MASK, (f)))\n+\n+/*\n+ * n indicates number of pins in the port, a is the register index\n+ * and f is pin configuration capabilities supported.\n+ */\n+#define RZG2L_GPIO_PORT_PACK(n, a, f)\tRZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f))\n \n /*\n * BIT(63) indicates dedicated pin, p is the register index while\n@@ -200,6 +208,18 @@ struct rzg2l_dedicated_configs {\n \tu64 config;\n };\n \n+/**\n+ * struct rzg2l_variable_pin_cfg - pin data cfg\n+ * @cfg: port pin configuration\n+ * @port: port number\n+ * @pin: port pin\n+ */\n+struct rzg2l_variable_pin_cfg {\n+\tu32 cfg:20;\n+\tu8 port:5;\n+\tu8 pin:5;\n+};\n+\n struct rzg2l_pinctrl_data {\n \tconst char * const *port_pins;\n \tconst u64 *port_pin_configs;\n@@ -208,6 +228,8 @@ struct rzg2l_pinctrl_data {\n \tunsigned int n_port_pins;\n \tunsigned int n_dedicated_pins;\n \tconst struct rzg2l_hwcfg *hwcfg;\n+\tconst struct rzg2l_variable_pin_cfg *variable_pin_cfg;\n+\tunsigned int n_variable_pin_cfg;\n };\n \n /**\n@@ -243,6 +265,143 @@ struct rzg2l_pinctrl {\n \n static const u16 available_ps[] = { 1800, 2500, 3300 };\n \n+#ifdef CONFIG_RISCV\n+static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl,\n+\t\t\t\t\t u64 pincfg,\n+\t\t\t\t\t unsigned int port,\n+\t\t\t\t\t u8 pin)\n+{\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) {\n+\t\tif (pctrl->data->variable_pin_cfg[i].port == port &&\n+\t\t pctrl->data->variable_pin_cfg[i].pin == pin)\n+\t\t\treturn (pincfg & ~PIN_CFG_VARIABLE) | pctrl->data->variable_pin_cfg[i].cfg;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] = {\n+\t{\n+\t\t.port = 20,\n+\t\t.pin = 0,\n+\t\t.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |\n+\t\t PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,\n+\t},\n+\t{\n+\t\t.port = 20,\n+\t\t.pin = 1,\n+\t\t.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |\n+\t\t PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,\n+\t},\n+\t{\n+\t\t.port = 20,\n+\t\t.pin = 2,\n+\t\t.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |\n+\t\t PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,\n+\t},\n+\t{\n+\t\t.port = 20,\n+\t\t.pin = 3,\n+\t\t.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,\n+\t},\n+\t{\n+\t\t.port = 20,\n+\t\t.pin = 4,\n+\t\t.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,\n+\t},\n+\t{\n+\t\t.port = 20,\n+\t\t.pin = 5,\n+\t\t.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,\n+\t},\n+\t{\n+\t\t.port = 20,\n+\t\t.pin = 6,\n+\t\t.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,\n+\t},\n+\t{\n+\t\t.port = 20,\n+\t\t.pin = 7,\n+\t\t.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t PIN_CFG_IEN | PIN_CFG_NOGPIO_INT,\n+\t},\n+\t{\n+\t\t.port = 23,\n+\t\t.pin = 1,\n+\t\t.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t PIN_CFG_NOGPIO_INT\n+\t},\n+\t{\n+\t\t.port = 23,\n+\t\t.pin = 2,\n+\t\t.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t PIN_CFG_NOGPIO_INT,\n+\t},\n+\t{\n+\t\t.port = 23,\n+\t\t.pin = 3,\n+\t\t.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t PIN_CFG_NOGPIO_INT,\n+\t},\n+\t{\n+\t\t.port = 23,\n+\t\t.pin = 4,\n+\t\t.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t PIN_CFG_NOGPIO_INT,\n+\t},\n+\t{\n+\t\t.port = 23,\n+\t\t.pin = 5,\n+\t\t.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT,\n+\t},\n+\t{\n+\t\t.port = 24,\n+\t\t.pin = 0,\n+\t\t.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT,\n+\t},\n+\t{\n+\t\t.port = 24,\n+\t\t.pin = 1,\n+\t\t.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t PIN_CFG_NOGPIO_INT,\n+\t},\n+\t{\n+\t\t.port = 24,\n+\t\t.pin = 2,\n+\t\t.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t PIN_CFG_NOGPIO_INT,\n+\t},\n+\t{\n+\t\t.port = 24,\n+\t\t.pin = 3,\n+\t\t.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t PIN_CFG_NOGPIO_INT,\n+\t},\n+\t{\n+\t\t.port = 24,\n+\t\t.pin = 4,\n+\t\t.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t PIN_CFG_NOGPIO_INT,\n+\t},\n+\t{\n+\t\t.port = 24,\n+\t\t.pin = 5,\n+\t\t.cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |\n+\t\t PIN_CFG_NOGPIO_INT,\n+\t},\n+};\n+#endif\n+\n static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,\n \t\t\t\t u8 pin, u8 off, u8 func)\n {\n@@ -1446,6 +1605,25 @@ static const u64 r9a07g043_gpio_configs[] = {\n \tRZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS),\n \tRZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS),\n \tRZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS),\n+#ifdef CONFIG_RISCV\n+\t/* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */\n+\tRZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t\t\t PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |\n+\t\t\t\t PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),\t\t\t/* P19 */\n+\tRZG2L_GPIO_PORT_PACK(8, 0x07, PIN_CFG_VARIABLE),\t\t\t\t/* P20 */\n+\tRZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t\t\t PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),\t\t\t/* P21 */\n+\tRZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD |\n+\t\t\t PIN_CFG_IEN | PIN_CFG_NOGPIO_INT),\t\t\t\t/* P22 */\n+\tRZG2L_GPIO_PORT_SPARSE_PACK(0x3e, 0x0a, PIN_CFG_VARIABLE),\t\t\t/* P23 */\n+\tRZG2L_GPIO_PORT_PACK(6, 0x0b, PIN_CFG_VARIABLE),\t\t\t\t/* P24 */\n+\tRZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_FILONOFF |\n+\t\t\t\t PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL |\n+\t\t\t\t PIN_CFG_NOGPIO_INT),\t\t\t\t/* P25 */\n+\t0x0,\t\t\t\t\t\t\t\t\t\t/* P26 */\n+\t0x0,\t\t\t\t\t\t\t\t\t\t/* P27 */\n+\tRZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO_INT),\t/* P28 */\n+#endif\n };\n \n static const u64 r9a08g045_gpio_configs[] = {\n@@ -1606,12 +1784,18 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = {\n \t\t\t\t\t\t PIN_CFG_IO_VMC_SD1)) },\n };\n \n-static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data)\n+static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl)\n {\n+\tconst struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq];\n+\tconst struct rzg2l_pinctrl_data *data = pctrl->data;\n+\tu64 *pin_data = pin_desc->drv_data;\n \tunsigned int gpioint;\n \tunsigned int i;\n \tu32 port, bit;\n \n+\tif (*pin_data & PIN_CFG_NOGPIO_INT)\n+\t\treturn -EINVAL;\n+\n \tport = virq / 8;\n \tbit = virq % 8;\n \n@@ -1721,7 +1905,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc,\n \tunsigned long flags;\n \tint gpioint, irq;\n \n-\tgpioint = rzg2l_gpio_get_gpioint(child, pctrl->data);\n+\tgpioint = rzg2l_gpio_get_gpioint(child, pctrl);\n \tif (gpioint < 0)\n \t\treturn gpioint;\n \n@@ -1907,6 +2091,13 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl)\n \t\tif (i && !(i % RZG2L_PINS_PER_PORT))\n \t\t\tj++;\n \t\tpin_data[i] = pctrl->data->port_pin_configs[j];\n+#ifdef CONFIG_RISCV\n+\t\tif (pin_data[i] & PIN_CFG_VARIABLE)\n+\t\t\tpin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl,\n+\t\t\t\t\t\t\t\t\t pin_data[i],\n+\t\t\t\t\t\t\t\t\t j,\n+\t\t\t\t\t\t\t\t\t i % RZG2L_PINS_PER_PORT);\n+#endif\n \t\tpins[i].drv_data = &pin_data[i];\n \t}\n \n@@ -2058,6 +2249,10 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {\n \t.n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT,\n \t.n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common),\n \t.hwcfg = &rzg2l_hwcfg,\n+#ifdef CONFIG_RISCV\n+\t.variable_pin_cfg = r9a07g043f_variable_pin_cfg,\n+\t.n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg),\n+#endif\n };\n \n static struct rzg2l_pinctrl_data r9a07g044_data = {\n", "prefixes": [ "v4", "3/4" ] }