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GET /api/patches/1483911/?format=api
{ "id": 1483911, "url": "http://patchwork.ozlabs.org/api/patches/1483911/?format=api", "web_url": "http://patchwork.ozlabs.org/project/rtc-linux/patch/1622011927-359-6-git-send-email-hsin-hsiung.wang@mediatek.com/", "project": { "id": 9, "url": "http://patchwork.ozlabs.org/api/projects/9/?format=api", "name": "Linux RTC development", "link_name": "rtc-linux", "list_id": "linux-rtc.vger.kernel.org", "list_email": "linux-rtc@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1622011927-359-6-git-send-email-hsin-hsiung.wang@mediatek.com>", "list_archive_url": null, "date": "2021-05-26T06:52:04", "name": "[v8,5/8] mfd: Add support for the MediaTek MT6359 PMIC", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "8ae75c8d279d2bb09c73ea3916e5d7f4db1f7cbe", "submitter": { "id": 74946, "url": "http://patchwork.ozlabs.org/api/people/74946/?format=api", "name": "Hsin-Hsiung Wang", "email": "hsin-hsiung.wang@mediatek.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/rtc-linux/patch/1622011927-359-6-git-send-email-hsin-hsiung.wang@mediatek.com/mbox/", "series": [ { "id": 245778, "url": "http://patchwork.ozlabs.org/api/series/245778/?format=api", "web_url": "http://patchwork.ozlabs.org/project/rtc-linux/list/?series=245778", "date": "2021-05-26T06:52:02", "name": "Add Support for MediaTek PMIC MT6359", "version": 8, "mbox": "http://patchwork.ozlabs.org/series/245778/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1483911/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1483911/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-rtc-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=23.128.96.18; helo=vger.kernel.org;\n envelope-from=linux-rtc-owner@vger.kernel.org; receiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [23.128.96.18])\n\tby ozlabs.org (Postfix) with ESMTP id 4FqhTS069Hz9sW7\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 26 May 2021 16:52:28 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n id S232976AbhEZGxz (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n Wed, 26 May 2021 02:53:55 -0400", "from mailgw01.mediatek.com ([210.61.82.183]:37230 \"EHLO\n mailgw01.mediatek.com\" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org\n with ESMTP id S232913AbhEZGxu (ORCPT\n <rfc822;linux-rtc@vger.kernel.org>); Wed, 26 May 2021 02:53:50 -0400", "from mtkcas10.mediatek.inc [(172.21.101.39)] by\n mailgw01.mediatek.com\n (envelope-from <hsin-hsiung.wang@mediatek.com>)\n (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256)\n with ESMTP id 1885081432; Wed, 26 May 2021 14:52:14 +0800", "from mtkcas11.mediatek.inc (172.21.101.40) by\n mtkmbs06n2.mediatek.inc (172.21.101.130) with Microsoft SMTP Server (TLS) id\n 15.0.1497.2; Wed, 26 May 2021 14:52:12 +0800", "from mtksdaap41.mediatek.inc (172.21.77.4) by mtkcas11.mediatek.inc\n (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend\n Transport; Wed, 26 May 2021 14:52:12 +0800" ], "X-UUID": [ "1990c4a244484ad7b15753241795b10d-20210526", "1990c4a244484ad7b15753241795b10d-20210526" ], "From": "Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>", "To": "Lee Jones <lee.jones@linaro.org>, Rob Herring <robh+dt@kernel.org>,\n Matthias Brugger <matthias.bgg@gmail.com>,\n Liam Girdwood <lgirdwood@gmail.com>,\n Mark Brown <broonie@kernel.org>,\n Eddie Huang <eddie.huang@mediatek.com>,\n Alessandro Zummo <a.zummo@towertech.it>,\n Alexandre Belloni <alexandre.belloni@bootlin.com>,\n Fei Shao <fshao@chromium.org>", "CC": "Sean Wang <sean.wang@mediatek.com>,\n Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>,\n Yuchen Huang <yuchen.huang@mediatek.com>,\n <devicetree@vger.kernel.org>,\n <linux-arm-kernel@lists.infradead.org>,\n <linux-mediatek@lists.infradead.org>,\n <linux-kernel@vger.kernel.org>, <linux-rtc@vger.kernel.org>,\n <srv_heupstream@mediatek.com>,\n <Project_Global_Chrome_Upstream_Group@mediatek.com>", "Subject": "[PATCH v8 5/8] mfd: Add support for the MediaTek MT6359 PMIC", "Date": "Wed, 26 May 2021 14:52:04 +0800", "Message-ID": "<1622011927-359-6-git-send-email-hsin-hsiung.wang@mediatek.com>", "X-Mailer": "git-send-email 2.6.4", "In-Reply-To": "<1622011927-359-1-git-send-email-hsin-hsiung.wang@mediatek.com>", "References": "<1622011927-359-1-git-send-email-hsin-hsiung.wang@mediatek.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MTK": "N", "Precedence": "bulk", "List-ID": "<linux-rtc.vger.kernel.org>", "X-Mailing-List": "linux-rtc@vger.kernel.org" }, "content": "This adds support for the MediaTek MT6359 PMIC. This is a\nmultifunction device with the following sub modules:\n\n- Codec\n- Interrupt\n- Regulator\n- RTC\n\nIt is interfaced to the host controller using SPI interface\nby a proprietary hardware called PMIC wrapper or pwrap.\nMT6359 MFD is a child device of the pwrap.\n\nSigned-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>\nAcked-for-MFD-by: Lee Jones <lee.jones@linaro.org>\n---\nchanges since v7:\n- no change.\n---\n drivers/mfd/mt6358-irq.c | 24 ++\n drivers/mfd/mt6397-core.c | 24 ++\n include/linux/mfd/mt6359/core.h | 133 +++++++++\n include/linux/mfd/mt6359/registers.h | 529 +++++++++++++++++++++++++++++++++++\n include/linux/mfd/mt6397/core.h | 1 +\n 5 files changed, 711 insertions(+)\n create mode 100644 include/linux/mfd/mt6359/core.h\n create mode 100644 include/linux/mfd/mt6359/registers.h", "diff": "diff --git a/drivers/mfd/mt6358-irq.c b/drivers/mfd/mt6358-irq.c\nindex 4b094e5..83f3ffbd 100644\n--- a/drivers/mfd/mt6358-irq.c\n+++ b/drivers/mfd/mt6358-irq.c\n@@ -5,6 +5,8 @@\n #include <linux/interrupt.h>\n #include <linux/mfd/mt6358/core.h>\n #include <linux/mfd/mt6358/registers.h>\n+#include <linux/mfd/mt6359/core.h>\n+#include <linux/mfd/mt6359/registers.h>\n #include <linux/mfd/mt6397/core.h>\n #include <linux/module.h>\n #include <linux/of.h>\n@@ -26,6 +28,17 @@ static const struct irq_top_t mt6358_ints[] = {\n \tMT6358_TOP_GEN(MISC),\n };\n \n+static const struct irq_top_t mt6359_ints[] = {\n+\tMT6359_TOP_GEN(BUCK),\n+\tMT6359_TOP_GEN(LDO),\n+\tMT6359_TOP_GEN(PSC),\n+\tMT6359_TOP_GEN(SCK),\n+\tMT6359_TOP_GEN(BM),\n+\tMT6359_TOP_GEN(HK),\n+\tMT6359_TOP_GEN(AUD),\n+\tMT6359_TOP_GEN(MISC),\n+};\n+\n static struct pmic_irq_data mt6358_irqd = {\n \t.num_top = ARRAY_SIZE(mt6358_ints),\n \t.num_pmic_irqs = MT6358_IRQ_NR,\n@@ -33,6 +46,13 @@ static struct pmic_irq_data mt6358_irqd = {\n \t.pmic_ints = mt6358_ints,\n };\n \n+static struct pmic_irq_data mt6359_irqd = {\n+\t.num_top = ARRAY_SIZE(mt6359_ints),\n+\t.num_pmic_irqs = MT6359_IRQ_NR,\n+\t.top_int_status_reg = MT6359_TOP_INT_STATUS0,\n+\t.pmic_ints = mt6359_ints,\n+};\n+\n static void pmic_irq_enable(struct irq_data *data)\n {\n \tunsigned int hwirq = irqd_to_hwirq(data);\n@@ -195,6 +215,10 @@ int mt6358_irq_init(struct mt6397_chip *chip)\n \t\tchip->irq_data = &mt6358_irqd;\n \t\tbreak;\n \n+\tcase MT6359_CHIP_ID:\n+\t\tchip->irq_data = &mt6359_irqd;\n+\t\tbreak;\n+\n \tdefault:\n \t\tdev_err(chip->dev, \"unsupported chip: 0x%x\\n\", chip->chip_id);\n \t\treturn -ENODEV;\ndiff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c\nindex 7518d74..9a615f7 100644\n--- a/drivers/mfd/mt6397-core.c\n+++ b/drivers/mfd/mt6397-core.c\n@@ -13,9 +13,11 @@\n #include <linux/mfd/core.h>\n #include <linux/mfd/mt6323/core.h>\n #include <linux/mfd/mt6358/core.h>\n+#include <linux/mfd/mt6359/core.h>\n #include <linux/mfd/mt6397/core.h>\n #include <linux/mfd/mt6323/registers.h>\n #include <linux/mfd/mt6358/registers.h>\n+#include <linux/mfd/mt6359/registers.h>\n #include <linux/mfd/mt6397/registers.h>\n \n #define MT6323_RTC_BASE\t\t0x8000\n@@ -99,6 +101,17 @@ static const struct mfd_cell mt6358_devs[] = {\n \t},\n };\n \n+static const struct mfd_cell mt6359_devs[] = {\n+\t{ .name = \"mt6359-regulator\", },\n+\t{\n+\t\t.name = \"mt6359-rtc\",\n+\t\t.num_resources = ARRAY_SIZE(mt6358_rtc_resources),\n+\t\t.resources = mt6358_rtc_resources,\n+\t\t.of_compatible = \"mediatek,mt6358-rtc\",\n+\t},\n+\t{ .name = \"mt6359-sound\", },\n+};\n+\n static const struct mfd_cell mt6397_devs[] = {\n \t{\n \t\t.name = \"mt6397-rtc\",\n@@ -149,6 +162,14 @@ static const struct chip_data mt6358_core = {\n \t.irq_init = mt6358_irq_init,\n };\n \n+static const struct chip_data mt6359_core = {\n+\t.cid_addr = MT6359_SWCID,\n+\t.cid_shift = 8,\n+\t.cells = mt6359_devs,\n+\t.cell_size = ARRAY_SIZE(mt6359_devs),\n+\t.irq_init = mt6358_irq_init,\n+};\n+\n static const struct chip_data mt6397_core = {\n \t.cid_addr = MT6397_CID,\n \t.cid_shift = 0,\n@@ -219,6 +240,9 @@ static const struct of_device_id mt6397_of_match[] = {\n \t\t.compatible = \"mediatek,mt6358\",\n \t\t.data = &mt6358_core,\n \t}, {\n+\t\t.compatible = \"mediatek,mt6359\",\n+\t\t.data = &mt6359_core,\n+\t}, {\n \t\t.compatible = \"mediatek,mt6397\",\n \t\t.data = &mt6397_core,\n \t}, {\ndiff --git a/include/linux/mfd/mt6359/core.h b/include/linux/mfd/mt6359/core.h\nnew file mode 100644\nindex 0000000..8d29886\n--- /dev/null\n+++ b/include/linux/mfd/mt6359/core.h\n@@ -0,0 +1,133 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2021 MediaTek Inc.\n+ */\n+\n+#ifndef __MFD_MT6359_CORE_H__\n+#define __MFD_MT6359_CORE_H__\n+\n+enum mt6359_irq_top_status_shift {\n+\tMT6359_BUCK_TOP = 0,\n+\tMT6359_LDO_TOP,\n+\tMT6359_PSC_TOP,\n+\tMT6359_SCK_TOP,\n+\tMT6359_BM_TOP,\n+\tMT6359_HK_TOP,\n+\tMT6359_AUD_TOP = 7,\n+\tMT6359_MISC_TOP,\n+};\n+\n+enum mt6359_irq_numbers {\n+\tMT6359_IRQ_VCORE_OC = 1,\n+\tMT6359_IRQ_VGPU11_OC,\n+\tMT6359_IRQ_VGPU12_OC,\n+\tMT6359_IRQ_VMODEM_OC,\n+\tMT6359_IRQ_VPROC1_OC,\n+\tMT6359_IRQ_VPROC2_OC,\n+\tMT6359_IRQ_VS1_OC,\n+\tMT6359_IRQ_VS2_OC,\n+\tMT6359_IRQ_VPA_OC = 9,\n+\tMT6359_IRQ_VFE28_OC = 16,\n+\tMT6359_IRQ_VXO22_OC,\n+\tMT6359_IRQ_VRF18_OC,\n+\tMT6359_IRQ_VRF12_OC,\n+\tMT6359_IRQ_VEFUSE_OC,\n+\tMT6359_IRQ_VCN33_1_OC,\n+\tMT6359_IRQ_VCN33_2_OC,\n+\tMT6359_IRQ_VCN13_OC,\n+\tMT6359_IRQ_VCN18_OC,\n+\tMT6359_IRQ_VA09_OC,\n+\tMT6359_IRQ_VCAMIO_OC,\n+\tMT6359_IRQ_VA12_OC,\n+\tMT6359_IRQ_VAUX18_OC,\n+\tMT6359_IRQ_VAUD18_OC,\n+\tMT6359_IRQ_VIO18_OC,\n+\tMT6359_IRQ_VSRAM_PROC1_OC,\n+\tMT6359_IRQ_VSRAM_PROC2_OC,\n+\tMT6359_IRQ_VSRAM_OTHERS_OC,\n+\tMT6359_IRQ_VSRAM_MD_OC,\n+\tMT6359_IRQ_VEMC_OC,\n+\tMT6359_IRQ_VSIM1_OC,\n+\tMT6359_IRQ_VSIM2_OC,\n+\tMT6359_IRQ_VUSB_OC,\n+\tMT6359_IRQ_VRFCK_OC,\n+\tMT6359_IRQ_VBBCK_OC,\n+\tMT6359_IRQ_VBIF28_OC,\n+\tMT6359_IRQ_VIBR_OC,\n+\tMT6359_IRQ_VIO28_OC,\n+\tMT6359_IRQ_VM18_OC,\n+\tMT6359_IRQ_VUFS_OC = 45,\n+\tMT6359_IRQ_PWRKEY = 48,\n+\tMT6359_IRQ_HOMEKEY,\n+\tMT6359_IRQ_PWRKEY_R,\n+\tMT6359_IRQ_HOMEKEY_R,\n+\tMT6359_IRQ_NI_LBAT_INT,\n+\tMT6359_IRQ_CHRDET_EDGE = 53,\n+\tMT6359_IRQ_RTC = 64,\n+\tMT6359_IRQ_FG_BAT_H = 80,\n+\tMT6359_IRQ_FG_BAT_L,\n+\tMT6359_IRQ_FG_CUR_H,\n+\tMT6359_IRQ_FG_CUR_L,\n+\tMT6359_IRQ_FG_ZCV = 84,\n+\tMT6359_IRQ_FG_N_CHARGE_L = 87,\n+\tMT6359_IRQ_FG_IAVG_H,\n+\tMT6359_IRQ_FG_IAVG_L = 89,\n+\tMT6359_IRQ_FG_DISCHARGE = 91,\n+\tMT6359_IRQ_FG_CHARGE,\n+\tMT6359_IRQ_BATON_LV = 96,\n+\tMT6359_IRQ_BATON_BAT_IN = 98,\n+\tMT6359_IRQ_BATON_BAT_OU,\n+\tMT6359_IRQ_BIF = 100,\n+\tMT6359_IRQ_BAT_H = 112,\n+\tMT6359_IRQ_BAT_L,\n+\tMT6359_IRQ_BAT2_H,\n+\tMT6359_IRQ_BAT2_L,\n+\tMT6359_IRQ_BAT_TEMP_H,\n+\tMT6359_IRQ_BAT_TEMP_L,\n+\tMT6359_IRQ_THR_H,\n+\tMT6359_IRQ_THR_L,\n+\tMT6359_IRQ_AUXADC_IMP,\n+\tMT6359_IRQ_NAG_C_DLTV = 121,\n+\tMT6359_IRQ_AUDIO = 128,\n+\tMT6359_IRQ_ACCDET = 133,\n+\tMT6359_IRQ_ACCDET_EINT0,\n+\tMT6359_IRQ_ACCDET_EINT1,\n+\tMT6359_IRQ_SPI_CMD_ALERT = 144,\n+\tMT6359_IRQ_NR,\n+};\n+\n+#define MT6359_IRQ_BUCK_BASE MT6359_IRQ_VCORE_OC\n+#define MT6359_IRQ_LDO_BASE MT6359_IRQ_VFE28_OC\n+#define MT6359_IRQ_PSC_BASE MT6359_IRQ_PWRKEY\n+#define MT6359_IRQ_SCK_BASE MT6359_IRQ_RTC\n+#define MT6359_IRQ_BM_BASE MT6359_IRQ_FG_BAT_H\n+#define MT6359_IRQ_HK_BASE MT6359_IRQ_BAT_H\n+#define MT6359_IRQ_AUD_BASE MT6359_IRQ_AUDIO\n+#define MT6359_IRQ_MISC_BASE MT6359_IRQ_SPI_CMD_ALERT\n+\n+#define MT6359_IRQ_BUCK_BITS (MT6359_IRQ_VPA_OC - MT6359_IRQ_BUCK_BASE + 1)\n+#define MT6359_IRQ_LDO_BITS (MT6359_IRQ_VUFS_OC - MT6359_IRQ_LDO_BASE + 1)\n+#define MT6359_IRQ_PSC_BITS\t\\\n+\t(MT6359_IRQ_CHRDET_EDGE - MT6359_IRQ_PSC_BASE + 1)\n+#define MT6359_IRQ_SCK_BITS (MT6359_IRQ_RTC - MT6359_IRQ_SCK_BASE + 1)\n+#define MT6359_IRQ_BM_BITS (MT6359_IRQ_BIF - MT6359_IRQ_BM_BASE + 1)\n+#define MT6359_IRQ_HK_BITS (MT6359_IRQ_NAG_C_DLTV - MT6359_IRQ_HK_BASE + 1)\n+#define MT6359_IRQ_AUD_BITS\t\\\n+\t(MT6359_IRQ_ACCDET_EINT1 - MT6359_IRQ_AUD_BASE + 1)\n+#define MT6359_IRQ_MISC_BITS\t\\\n+\t(MT6359_IRQ_SPI_CMD_ALERT - MT6359_IRQ_MISC_BASE + 1)\n+\n+#define MT6359_TOP_GEN(sp)\t\\\n+{\t\\\n+\t.hwirq_base = MT6359_IRQ_##sp##_BASE,\t\\\n+\t.num_int_regs =\t\\\n+\t\t((MT6359_IRQ_##sp##_BITS - 1) /\t\\\n+\t\tMTK_PMIC_REG_WIDTH) + 1,\t\\\n+\t.en_reg = MT6359_##sp##_TOP_INT_CON0,\t\\\n+\t.en_reg_shift = 0x6,\t\\\n+\t.sta_reg = MT6359_##sp##_TOP_INT_STATUS0,\t\\\n+\t.sta_reg_shift = 0x2,\t\\\n+\t.top_offset = MT6359_##sp##_TOP,\t\\\n+}\n+\n+#endif /* __MFD_MT6359_CORE_H__ */\ndiff --git a/include/linux/mfd/mt6359/registers.h b/include/linux/mfd/mt6359/registers.h\nnew file mode 100644\nindex 0000000..2135c96\n--- /dev/null\n+++ b/include/linux/mfd/mt6359/registers.h\n@@ -0,0 +1,529 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2021 MediaTek Inc.\n+ */\n+\n+#ifndef __MFD_MT6359_REGISTERS_H__\n+#define __MFD_MT6359_REGISTERS_H__\n+\n+/* PMIC Registers */\n+#define MT6359_SWCID 0xa\n+#define MT6359_MISC_TOP_INT_CON0 0x188\n+#define MT6359_MISC_TOP_INT_STATUS0 0x194\n+#define MT6359_TOP_INT_STATUS0 0x19e\n+#define MT6359_SCK_TOP_INT_CON0 0x528\n+#define MT6359_SCK_TOP_INT_STATUS0 0x534\n+#define MT6359_EOSC_CALI_CON0 0x53a\n+#define MT6359_EOSC_CALI_CON1 0x53c\n+#define MT6359_RTC_MIX_CON0 0x53e\n+#define MT6359_RTC_MIX_CON1 0x540\n+#define MT6359_RTC_MIX_CON2 0x542\n+#define MT6359_RTC_DSN_ID 0x580\n+#define MT6359_RTC_DSN_REV0 0x582\n+#define MT6359_RTC_DBI 0x584\n+#define MT6359_RTC_DXI 0x586\n+#define MT6359_RTC_BBPU 0x588\n+#define MT6359_RTC_IRQ_STA 0x58a\n+#define MT6359_RTC_IRQ_EN 0x58c\n+#define MT6359_RTC_CII_EN 0x58e\n+#define MT6359_RTC_AL_MASK 0x590\n+#define MT6359_RTC_TC_SEC 0x592\n+#define MT6359_RTC_TC_MIN 0x594\n+#define MT6359_RTC_TC_HOU 0x596\n+#define MT6359_RTC_TC_DOM 0x598\n+#define MT6359_RTC_TC_DOW 0x59a\n+#define MT6359_RTC_TC_MTH 0x59c\n+#define MT6359_RTC_TC_YEA 0x59e\n+#define MT6359_RTC_AL_SEC 0x5a0\n+#define MT6359_RTC_AL_MIN 0x5a2\n+#define MT6359_RTC_AL_HOU 0x5a4\n+#define MT6359_RTC_AL_DOM 0x5a6\n+#define MT6359_RTC_AL_DOW 0x5a8\n+#define MT6359_RTC_AL_MTH 0x5aa\n+#define MT6359_RTC_AL_YEA 0x5ac\n+#define MT6359_RTC_OSC32CON 0x5ae\n+#define MT6359_RTC_POWERKEY1 0x5b0\n+#define MT6359_RTC_POWERKEY2 0x5b2\n+#define MT6359_RTC_PDN1 0x5b4\n+#define MT6359_RTC_PDN2 0x5b6\n+#define MT6359_RTC_SPAR0 0x5b8\n+#define MT6359_RTC_SPAR1 0x5ba\n+#define MT6359_RTC_PROT 0x5bc\n+#define MT6359_RTC_DIFF 0x5be\n+#define MT6359_RTC_CALI 0x5c0\n+#define MT6359_RTC_WRTGR 0x5c2\n+#define MT6359_RTC_CON 0x5c4\n+#define MT6359_RTC_SEC_CTRL 0x5c6\n+#define MT6359_RTC_INT_CNT 0x5c8\n+#define MT6359_RTC_SEC_DAT0 0x5ca\n+#define MT6359_RTC_SEC_DAT1 0x5cc\n+#define MT6359_RTC_SEC_DAT2 0x5ce\n+#define MT6359_RTC_SEC_DSN_ID 0x600\n+#define MT6359_RTC_SEC_DSN_REV0 0x602\n+#define MT6359_RTC_SEC_DBI 0x604\n+#define MT6359_RTC_SEC_DXI 0x606\n+#define MT6359_RTC_TC_SEC_SEC 0x608\n+#define MT6359_RTC_TC_MIN_SEC 0x60a\n+#define MT6359_RTC_TC_HOU_SEC 0x60c\n+#define MT6359_RTC_TC_DOM_SEC 0x60e\n+#define MT6359_RTC_TC_DOW_SEC 0x610\n+#define MT6359_RTC_TC_MTH_SEC 0x612\n+#define MT6359_RTC_TC_YEA_SEC 0x614\n+#define MT6359_RTC_SEC_CK_PDN 0x616\n+#define MT6359_RTC_SEC_WRTGR 0x618\n+#define MT6359_PSC_TOP_INT_CON0 0x910\n+#define MT6359_PSC_TOP_INT_STATUS0 0x91c\n+#define MT6359_BM_TOP_INT_CON0 0xc32\n+#define MT6359_BM_TOP_INT_CON1 0xc38\n+#define MT6359_BM_TOP_INT_STATUS0 0xc4a\n+#define MT6359_BM_TOP_INT_STATUS1 0xc4c\n+#define MT6359_HK_TOP_INT_CON0 0xf92\n+#define MT6359_HK_TOP_INT_STATUS0 0xf9e\n+#define MT6359_BUCK_TOP_INT_CON0 0x1418\n+#define MT6359_BUCK_TOP_INT_STATUS0 0x1424\n+#define MT6359_BUCK_VPU_CON0 0x1488\n+#define MT6359_BUCK_VPU_DBG0 0x14a6\n+#define MT6359_BUCK_VPU_DBG1 0x14a8\n+#define MT6359_BUCK_VPU_ELR0 0x14ac\n+#define MT6359_BUCK_VCORE_CON0 0x1508\n+#define MT6359_BUCK_VCORE_DBG0 0x1526\n+#define MT6359_BUCK_VCORE_DBG1 0x1528\n+#define MT6359_BUCK_VCORE_SSHUB_CON0 0x152a\n+#define MT6359_BUCK_VCORE_ELR0 0x1534\n+#define MT6359_BUCK_VGPU11_CON0 0x1588\n+#define MT6359_BUCK_VGPU11_DBG0 0x15a6\n+#define MT6359_BUCK_VGPU11_DBG1 0x15a8\n+#define MT6359_BUCK_VGPU11_ELR0 0x15ac\n+#define MT6359_BUCK_VMODEM_CON0 0x1688\n+#define MT6359_BUCK_VMODEM_DBG0 0x16a6\n+#define MT6359_BUCK_VMODEM_DBG1 0x16a8\n+#define MT6359_BUCK_VMODEM_ELR0 0x16ae\n+#define MT6359_BUCK_VPROC1_CON0 0x1708\n+#define MT6359_BUCK_VPROC1_DBG0 0x1726\n+#define MT6359_BUCK_VPROC1_DBG1 0x1728\n+#define MT6359_BUCK_VPROC1_ELR0 0x172e\n+#define MT6359_BUCK_VPROC2_CON0 0x1788\n+#define MT6359_BUCK_VPROC2_DBG0 0x17a6\n+#define MT6359_BUCK_VPROC2_DBG1 0x17a8\n+#define MT6359_BUCK_VPROC2_ELR0 0x17b2\n+#define MT6359_BUCK_VS1_CON0 0x1808\n+#define MT6359_BUCK_VS1_DBG0 0x1826\n+#define MT6359_BUCK_VS1_DBG1 0x1828\n+#define MT6359_BUCK_VS1_ELR0 0x1834\n+#define MT6359_BUCK_VS2_CON0 0x1888\n+#define MT6359_BUCK_VS2_DBG0 0x18a6\n+#define MT6359_BUCK_VS2_DBG1 0x18a8\n+#define MT6359_BUCK_VS2_ELR0 0x18b4\n+#define MT6359_BUCK_VPA_CON0 0x1908\n+#define MT6359_BUCK_VPA_CON1 0x190e\n+#define MT6359_BUCK_VPA_CFG0 0x1910\n+#define MT6359_BUCK_VPA_CFG1 0x1912\n+#define MT6359_BUCK_VPA_DBG0 0x1914\n+#define MT6359_BUCK_VPA_DBG1 0x1916\n+#define MT6359_VGPUVCORE_ANA_CON2 0x198e\n+#define MT6359_VGPUVCORE_ANA_CON13 0x19a4\n+#define MT6359_VPROC1_ANA_CON3 0x19b2\n+#define MT6359_VPROC2_ANA_CON3 0x1a0e\n+#define MT6359_VMODEM_ANA_CON3 0x1a1a\n+#define MT6359_VPU_ANA_CON3 0x1a26\n+#define MT6359_VS1_ANA_CON0 0x1a2c\n+#define MT6359_VS2_ANA_CON0 0x1a34\n+#define MT6359_VPA_ANA_CON0 0x1a3c\n+#define MT6359_LDO_TOP_INT_CON0 0x1b14\n+#define MT6359_LDO_TOP_INT_CON1 0x1b1a\n+#define MT6359_LDO_TOP_INT_STATUS0 0x1b28\n+#define MT6359_LDO_TOP_INT_STATUS1 0x1b2a\n+#define MT6359_LDO_VSRAM_PROC1_ELR 0x1b40\n+#define MT6359_LDO_VSRAM_PROC2_ELR 0x1b42\n+#define MT6359_LDO_VSRAM_OTHERS_ELR 0x1b44\n+#define MT6359_LDO_VSRAM_MD_ELR 0x1b46\n+#define MT6359_LDO_VFE28_CON0 0x1b88\n+#define MT6359_LDO_VFE28_MON 0x1b8a\n+#define MT6359_LDO_VXO22_CON0 0x1b98\n+#define MT6359_LDO_VXO22_MON 0x1b9a\n+#define MT6359_LDO_VRF18_CON0 0x1ba8\n+#define MT6359_LDO_VRF18_MON 0x1baa\n+#define MT6359_LDO_VRF12_CON0 0x1bb8\n+#define MT6359_LDO_VRF12_MON 0x1bba\n+#define MT6359_LDO_VEFUSE_CON0 0x1bc8\n+#define MT6359_LDO_VEFUSE_MON 0x1bca\n+#define MT6359_LDO_VCN33_1_CON0 0x1bd8\n+#define MT6359_LDO_VCN33_1_MON 0x1bda\n+#define MT6359_LDO_VCN33_1_MULTI_SW 0x1be8\n+#define MT6359_LDO_VCN33_2_CON0 0x1c08\n+#define MT6359_LDO_VCN33_2_MON 0x1c0a\n+#define MT6359_LDO_VCN33_2_MULTI_SW 0x1c18\n+#define MT6359_LDO_VCN13_CON0 0x1c1a\n+#define MT6359_LDO_VCN13_MON 0x1c1c\n+#define MT6359_LDO_VCN18_CON0 0x1c2a\n+#define MT6359_LDO_VCN18_MON 0x1c2c\n+#define MT6359_LDO_VA09_CON0 0x1c3a\n+#define MT6359_LDO_VA09_MON 0x1c3c\n+#define MT6359_LDO_VCAMIO_CON0 0x1c4a\n+#define MT6359_LDO_VCAMIO_MON 0x1c4c\n+#define MT6359_LDO_VA12_CON0 0x1c5a\n+#define MT6359_LDO_VA12_MON 0x1c5c\n+#define MT6359_LDO_VAUX18_CON0 0x1c88\n+#define MT6359_LDO_VAUX18_MON 0x1c8a\n+#define MT6359_LDO_VAUD18_CON0 0x1c98\n+#define MT6359_LDO_VAUD18_MON 0x1c9a\n+#define MT6359_LDO_VIO18_CON0 0x1ca8\n+#define MT6359_LDO_VIO18_MON 0x1caa\n+#define MT6359_LDO_VEMC_CON0 0x1cb8\n+#define MT6359_LDO_VEMC_MON 0x1cba\n+#define MT6359_LDO_VSIM1_CON0 0x1cc8\n+#define MT6359_LDO_VSIM1_MON 0x1cca\n+#define MT6359_LDO_VSIM2_CON0 0x1cd8\n+#define MT6359_LDO_VSIM2_MON 0x1cda\n+#define MT6359_LDO_VUSB_CON0 0x1d08\n+#define MT6359_LDO_VUSB_MON 0x1d0a\n+#define MT6359_LDO_VUSB_MULTI_SW 0x1d18\n+#define MT6359_LDO_VRFCK_CON0 0x1d1a\n+#define MT6359_LDO_VRFCK_MON 0x1d1c\n+#define MT6359_LDO_VBBCK_CON0 0x1d2a\n+#define MT6359_LDO_VBBCK_MON 0x1d2c\n+#define MT6359_LDO_VBIF28_CON0 0x1d3a\n+#define MT6359_LDO_VBIF28_MON 0x1d3c\n+#define MT6359_LDO_VIBR_CON0 0x1d4a\n+#define MT6359_LDO_VIBR_MON 0x1d4c\n+#define MT6359_LDO_VIO28_CON0 0x1d5a\n+#define MT6359_LDO_VIO28_MON 0x1d5c\n+#define MT6359_LDO_VM18_CON0 0x1d88\n+#define MT6359_LDO_VM18_MON 0x1d8a\n+#define MT6359_LDO_VUFS_CON0 0x1d98\n+#define MT6359_LDO_VUFS_MON 0x1d9a\n+#define MT6359_LDO_VSRAM_PROC1_CON0 0x1e88\n+#define MT6359_LDO_VSRAM_PROC1_MON 0x1e8a\n+#define MT6359_LDO_VSRAM_PROC1_VOSEL1 0x1e8e\n+#define MT6359_LDO_VSRAM_PROC2_CON0 0x1ea6\n+#define MT6359_LDO_VSRAM_PROC2_MON 0x1ea8\n+#define MT6359_LDO_VSRAM_PROC2_VOSEL1 0x1eac\n+#define MT6359_LDO_VSRAM_OTHERS_CON0 0x1f08\n+#define MT6359_LDO_VSRAM_OTHERS_MON 0x1f0a\n+#define MT6359_LDO_VSRAM_OTHERS_VOSEL1 0x1f0e\n+#define MT6359_LDO_VSRAM_OTHERS_SSHUB 0x1f26\n+#define MT6359_LDO_VSRAM_MD_CON0 0x1f2c\n+#define MT6359_LDO_VSRAM_MD_MON 0x1f2e\n+#define MT6359_LDO_VSRAM_MD_VOSEL1 0x1f32\n+#define MT6359_VFE28_ANA_CON0 0x1f88\n+#define MT6359_VAUX18_ANA_CON0 0x1f8c\n+#define MT6359_VUSB_ANA_CON0 0x1f90\n+#define MT6359_VBIF28_ANA_CON0 0x1f94\n+#define MT6359_VCN33_1_ANA_CON0 0x1f98\n+#define MT6359_VCN33_2_ANA_CON0 0x1f9c\n+#define MT6359_VEMC_ANA_CON0 0x1fa0\n+#define MT6359_VSIM1_ANA_CON0 0x1fa4\n+#define MT6359_VSIM2_ANA_CON0 0x1fa8\n+#define MT6359_VIO28_ANA_CON0 0x1fac\n+#define MT6359_VIBR_ANA_CON0 0x1fb0\n+#define MT6359_VRF18_ANA_CON0 0x2008\n+#define MT6359_VEFUSE_ANA_CON0 0x200c\n+#define MT6359_VCN18_ANA_CON0 0x2010\n+#define MT6359_VCAMIO_ANA_CON0 0x2014\n+#define MT6359_VAUD18_ANA_CON0 0x2018\n+#define MT6359_VIO18_ANA_CON0 0x201c\n+#define MT6359_VM18_ANA_CON0 0x2020\n+#define MT6359_VUFS_ANA_CON0 0x2024\n+#define MT6359_VRF12_ANA_CON0 0x202a\n+#define MT6359_VCN13_ANA_CON0 0x202e\n+#define MT6359_VA09_ANA_CON0 0x2032\n+#define MT6359_VA12_ANA_CON0 0x2036\n+#define MT6359_VXO22_ANA_CON0 0x2088\n+#define MT6359_VRFCK_ANA_CON0 0x208c\n+#define MT6359_VBBCK_ANA_CON0 0x2094\n+#define MT6359_AUD_TOP_INT_CON0 0x2328\n+#define MT6359_AUD_TOP_INT_STATUS0 0x2334\n+\n+#define MT6359_RG_BUCK_VPU_EN_ADDR MT6359_BUCK_VPU_CON0\n+#define MT6359_RG_BUCK_VPU_LP_ADDR MT6359_BUCK_VPU_CON0\n+#define MT6359_RG_BUCK_VPU_LP_SHIFT 1\n+#define MT6359_DA_VPU_VOSEL_ADDR MT6359_BUCK_VPU_DBG0\n+#define MT6359_DA_VPU_VOSEL_MASK 0x7F\n+#define MT6359_DA_VPU_VOSEL_SHIFT 0\n+#define MT6359_DA_VPU_EN_ADDR MT6359_BUCK_VPU_DBG1\n+#define MT6359_RG_BUCK_VPU_VOSEL_ADDR MT6359_BUCK_VPU_ELR0\n+#define MT6359_RG_BUCK_VPU_VOSEL_MASK 0x7F\n+#define MT6359_RG_BUCK_VPU_VOSEL_SHIFT 0\n+#define MT6359_RG_BUCK_VCORE_EN_ADDR MT6359_BUCK_VCORE_CON0\n+#define MT6359_RG_BUCK_VCORE_LP_ADDR MT6359_BUCK_VCORE_CON0\n+#define MT6359_RG_BUCK_VCORE_LP_SHIFT 1\n+#define MT6359_DA_VCORE_VOSEL_ADDR MT6359_BUCK_VCORE_DBG0\n+#define MT6359_DA_VCORE_VOSEL_MASK 0x7F\n+#define MT6359_DA_VCORE_VOSEL_SHIFT 0\n+#define MT6359_DA_VCORE_EN_ADDR MT6359_BUCK_VCORE_DBG1\n+#define MT6359_RG_BUCK_VCORE_SSHUB_EN_ADDR MT6359_BUCK_VCORE_SSHUB_CON0\n+#define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_ADDR MT6359_BUCK_VCORE_SSHUB_CON0\n+#define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_MASK 0x7F\n+#define MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_SHIFT 4\n+#define MT6359_RG_BUCK_VCORE_VOSEL_ADDR MT6359_BUCK_VCORE_ELR0\n+#define MT6359_RG_BUCK_VCORE_VOSEL_MASK 0x7F\n+#define MT6359_RG_BUCK_VCORE_VOSEL_SHIFT 0\n+#define MT6359_RG_BUCK_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_CON0\n+#define MT6359_RG_BUCK_VGPU11_LP_ADDR MT6359_BUCK_VGPU11_CON0\n+#define MT6359_RG_BUCK_VGPU11_LP_SHIFT 1\n+#define MT6359_DA_VGPU11_VOSEL_ADDR MT6359_BUCK_VGPU11_DBG0\n+#define MT6359_DA_VGPU11_VOSEL_MASK 0x7F\n+#define MT6359_DA_VGPU11_VOSEL_SHIFT 0\n+#define MT6359_DA_VGPU11_EN_ADDR MT6359_BUCK_VGPU11_DBG1\n+#define MT6359_RG_BUCK_VGPU11_VOSEL_ADDR MT6359_BUCK_VGPU11_ELR0\n+#define MT6359_RG_BUCK_VGPU11_VOSEL_MASK 0x7F\n+#define MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT 0\n+#define MT6359_RG_BUCK_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_CON0\n+#define MT6359_RG_BUCK_VMODEM_LP_ADDR MT6359_BUCK_VMODEM_CON0\n+#define MT6359_RG_BUCK_VMODEM_LP_SHIFT 1\n+#define MT6359_DA_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_DBG0\n+#define MT6359_DA_VMODEM_VOSEL_MASK 0x7F\n+#define MT6359_DA_VMODEM_VOSEL_SHIFT 0\n+#define MT6359_DA_VMODEM_EN_ADDR MT6359_BUCK_VMODEM_DBG1\n+#define MT6359_RG_BUCK_VMODEM_VOSEL_ADDR MT6359_BUCK_VMODEM_ELR0\n+#define MT6359_RG_BUCK_VMODEM_VOSEL_MASK 0x7F\n+#define MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT 0\n+#define MT6359_RG_BUCK_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_CON0\n+#define MT6359_RG_BUCK_VPROC1_LP_ADDR MT6359_BUCK_VPROC1_CON0\n+#define MT6359_RG_BUCK_VPROC1_LP_SHIFT 1\n+#define MT6359_DA_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_DBG0\n+#define MT6359_DA_VPROC1_VOSEL_MASK 0x7F\n+#define MT6359_DA_VPROC1_VOSEL_SHIFT 0\n+#define MT6359_DA_VPROC1_EN_ADDR MT6359_BUCK_VPROC1_DBG1\n+#define MT6359_RG_BUCK_VPROC1_VOSEL_ADDR MT6359_BUCK_VPROC1_ELR0\n+#define MT6359_RG_BUCK_VPROC1_VOSEL_MASK 0x7F\n+#define MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT 0\n+#define MT6359_RG_BUCK_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_CON0\n+#define MT6359_RG_BUCK_VPROC2_LP_ADDR MT6359_BUCK_VPROC2_CON0\n+#define MT6359_RG_BUCK_VPROC2_LP_SHIFT 1\n+#define MT6359_DA_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_DBG0\n+#define MT6359_DA_VPROC2_VOSEL_MASK 0x7F\n+#define MT6359_DA_VPROC2_VOSEL_SHIFT 0\n+#define MT6359_DA_VPROC2_EN_ADDR MT6359_BUCK_VPROC2_DBG1\n+#define MT6359_RG_BUCK_VPROC2_VOSEL_ADDR MT6359_BUCK_VPROC2_ELR0\n+#define MT6359_RG_BUCK_VPROC2_VOSEL_MASK 0x7F\n+#define MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT 0\n+#define MT6359_RG_BUCK_VS1_EN_ADDR MT6359_BUCK_VS1_CON0\n+#define MT6359_RG_BUCK_VS1_LP_ADDR MT6359_BUCK_VS1_CON0\n+#define MT6359_RG_BUCK_VS1_LP_SHIFT 1\n+#define MT6359_DA_VS1_VOSEL_ADDR MT6359_BUCK_VS1_DBG0\n+#define MT6359_DA_VS1_VOSEL_MASK 0x7F\n+#define MT6359_DA_VS1_VOSEL_SHIFT 0\n+#define MT6359_DA_VS1_EN_ADDR MT6359_BUCK_VS1_DBG1\n+#define MT6359_RG_BUCK_VS1_VOSEL_ADDR MT6359_BUCK_VS1_ELR0\n+#define MT6359_RG_BUCK_VS1_VOSEL_MASK 0x7F\n+#define MT6359_RG_BUCK_VS1_VOSEL_SHIFT 0\n+#define MT6359_RG_BUCK_VS2_EN_ADDR MT6359_BUCK_VS2_CON0\n+#define MT6359_RG_BUCK_VS2_LP_ADDR MT6359_BUCK_VS2_CON0\n+#define MT6359_RG_BUCK_VS2_LP_SHIFT 1\n+#define MT6359_DA_VS2_VOSEL_ADDR MT6359_BUCK_VS2_DBG0\n+#define MT6359_DA_VS2_VOSEL_MASK 0x7F\n+#define MT6359_DA_VS2_VOSEL_SHIFT 0\n+#define MT6359_DA_VS2_EN_ADDR MT6359_BUCK_VS2_DBG1\n+#define MT6359_RG_BUCK_VS2_VOSEL_ADDR MT6359_BUCK_VS2_ELR0\n+#define MT6359_RG_BUCK_VS2_VOSEL_MASK 0x7F\n+#define MT6359_RG_BUCK_VS2_VOSEL_SHIFT 0\n+#define MT6359_RG_BUCK_VPA_EN_ADDR MT6359_BUCK_VPA_CON0\n+#define MT6359_RG_BUCK_VPA_LP_ADDR MT6359_BUCK_VPA_CON0\n+#define MT6359_RG_BUCK_VPA_LP_SHIFT 1\n+#define MT6359_RG_BUCK_VPA_VOSEL_ADDR MT6359_BUCK_VPA_CON1\n+#define MT6359_RG_BUCK_VPA_VOSEL_MASK 0x3F\n+#define MT6359_RG_BUCK_VPA_VOSEL_SHIFT 0\n+#define MT6359_DA_VPA_VOSEL_ADDR MT6359_BUCK_VPA_DBG0\n+#define MT6359_DA_VPA_VOSEL_MASK 0x3F\n+#define MT6359_DA_VPA_VOSEL_SHIFT 0\n+#define MT6359_DA_VPA_EN_ADDR MT6359_BUCK_VPA_DBG1\n+#define MT6359_RG_VGPU11_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON2\n+#define MT6359_RG_VGPU11_FCCM_SHIFT 9\n+#define MT6359_RG_VCORE_FCCM_ADDR MT6359_VGPUVCORE_ANA_CON13\n+#define MT6359_RG_VCORE_FCCM_SHIFT 5\n+#define MT6359_RG_VPROC1_FCCM_ADDR MT6359_VPROC1_ANA_CON3\n+#define MT6359_RG_VPROC1_FCCM_SHIFT 1\n+#define MT6359_RG_VPROC2_FCCM_ADDR MT6359_VPROC2_ANA_CON3\n+#define MT6359_RG_VPROC2_FCCM_SHIFT 1\n+#define MT6359_RG_VMODEM_FCCM_ADDR MT6359_VMODEM_ANA_CON3\n+#define MT6359_RG_VMODEM_FCCM_SHIFT 1\n+#define MT6359_RG_VPU_FCCM_ADDR MT6359_VPU_ANA_CON3\n+#define MT6359_RG_VPU_FCCM_SHIFT 1\n+#define MT6359_RG_VS1_FPWM_ADDR MT6359_VS1_ANA_CON0\n+#define MT6359_RG_VS1_FPWM_SHIFT 3\n+#define MT6359_RG_VS2_FPWM_ADDR MT6359_VS2_ANA_CON0\n+#define MT6359_RG_VS2_FPWM_SHIFT 3\n+#define MT6359_RG_VPA_MODESET_ADDR MT6359_VPA_ANA_CON0\n+#define MT6359_RG_VPA_MODESET_SHIFT 1\n+#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_ADDR MT6359_LDO_VSRAM_PROC1_ELR\n+#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK 0x7F\n+#define MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT 0\n+#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_ADDR MT6359_LDO_VSRAM_PROC2_ELR\n+#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK 0x7F\n+#define MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT 0\n+#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_ELR\n+#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK 0x7F\n+#define MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT 0\n+#define MT6359_RG_LDO_VSRAM_MD_VOSEL_ADDR MT6359_LDO_VSRAM_MD_ELR\n+#define MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK 0x7F\n+#define MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT 0\n+#define MT6359_RG_LDO_VFE28_EN_ADDR MT6359_LDO_VFE28_CON0\n+#define MT6359_DA_VFE28_B_EN_ADDR MT6359_LDO_VFE28_MON\n+#define MT6359_RG_LDO_VXO22_EN_ADDR MT6359_LDO_VXO22_CON0\n+#define MT6359_RG_LDO_VXO22_EN_SHIFT 0\n+#define MT6359_DA_VXO22_B_EN_ADDR MT6359_LDO_VXO22_MON\n+#define MT6359_RG_LDO_VRF18_EN_ADDR MT6359_LDO_VRF18_CON0\n+#define MT6359_RG_LDO_VRF18_EN_SHIFT 0\n+#define MT6359_DA_VRF18_B_EN_ADDR MT6359_LDO_VRF18_MON\n+#define MT6359_RG_LDO_VRF12_EN_ADDR MT6359_LDO_VRF12_CON0\n+#define MT6359_RG_LDO_VRF12_EN_SHIFT 0\n+#define MT6359_DA_VRF12_B_EN_ADDR MT6359_LDO_VRF12_MON\n+#define MT6359_RG_LDO_VEFUSE_EN_ADDR MT6359_LDO_VEFUSE_CON0\n+#define MT6359_RG_LDO_VEFUSE_EN_SHIFT 0\n+#define MT6359_DA_VEFUSE_B_EN_ADDR MT6359_LDO_VEFUSE_MON\n+#define MT6359_RG_LDO_VCN33_1_EN_0_ADDR MT6359_LDO_VCN33_1_CON0\n+#define MT6359_RG_LDO_VCN33_1_EN_0_MASK 0x1\n+#define MT6359_RG_LDO_VCN33_1_EN_0_SHIFT 0\n+#define MT6359_DA_VCN33_1_B_EN_ADDR MT6359_LDO_VCN33_1_MON\n+#define MT6359_RG_LDO_VCN33_1_EN_1_ADDR MT6359_LDO_VCN33_1_MULTI_SW\n+#define MT6359_RG_LDO_VCN33_1_EN_1_SHIFT 15\n+#define MT6359_RG_LDO_VCN33_2_EN_0_ADDR MT6359_LDO_VCN33_2_CON0\n+#define MT6359_RG_LDO_VCN33_2_EN_0_SHIFT 0\n+#define MT6359_DA_VCN33_2_B_EN_ADDR MT6359_LDO_VCN33_2_MON\n+#define MT6359_RG_LDO_VCN33_2_EN_1_ADDR MT6359_LDO_VCN33_2_MULTI_SW\n+#define MT6359_RG_LDO_VCN33_2_EN_1_MASK 0x1\n+#define MT6359_RG_LDO_VCN33_2_EN_1_SHIFT 15\n+#define MT6359_RG_LDO_VCN13_EN_ADDR MT6359_LDO_VCN13_CON0\n+#define MT6359_RG_LDO_VCN13_EN_SHIFT 0\n+#define MT6359_DA_VCN13_B_EN_ADDR MT6359_LDO_VCN13_MON\n+#define MT6359_RG_LDO_VCN18_EN_ADDR MT6359_LDO_VCN18_CON0\n+#define MT6359_DA_VCN18_B_EN_ADDR MT6359_LDO_VCN18_MON\n+#define MT6359_RG_LDO_VA09_EN_ADDR MT6359_LDO_VA09_CON0\n+#define MT6359_RG_LDO_VA09_EN_SHIFT 0\n+#define MT6359_DA_VA09_B_EN_ADDR MT6359_LDO_VA09_MON\n+#define MT6359_RG_LDO_VCAMIO_EN_ADDR MT6359_LDO_VCAMIO_CON0\n+#define MT6359_RG_LDO_VCAMIO_EN_SHIFT 0\n+#define MT6359_DA_VCAMIO_B_EN_ADDR MT6359_LDO_VCAMIO_MON\n+#define MT6359_RG_LDO_VA12_EN_ADDR MT6359_LDO_VA12_CON0\n+#define MT6359_RG_LDO_VA12_EN_SHIFT 0\n+#define MT6359_DA_VA12_B_EN_ADDR MT6359_LDO_VA12_MON\n+#define MT6359_RG_LDO_VAUX18_EN_ADDR MT6359_LDO_VAUX18_CON0\n+#define MT6359_DA_VAUX18_B_EN_ADDR MT6359_LDO_VAUX18_MON\n+#define MT6359_RG_LDO_VAUD18_EN_ADDR MT6359_LDO_VAUD18_CON0\n+#define MT6359_DA_VAUD18_B_EN_ADDR MT6359_LDO_VAUD18_MON\n+#define MT6359_RG_LDO_VIO18_EN_ADDR MT6359_LDO_VIO18_CON0\n+#define MT6359_RG_LDO_VIO18_EN_SHIFT 0\n+#define MT6359_DA_VIO18_B_EN_ADDR MT6359_LDO_VIO18_MON\n+#define MT6359_RG_LDO_VEMC_EN_ADDR MT6359_LDO_VEMC_CON0\n+#define MT6359_RG_LDO_VEMC_EN_SHIFT 0\n+#define MT6359_DA_VEMC_B_EN_ADDR MT6359_LDO_VEMC_MON\n+#define MT6359_RG_LDO_VSIM1_EN_ADDR MT6359_LDO_VSIM1_CON0\n+#define MT6359_RG_LDO_VSIM1_EN_SHIFT 0\n+#define MT6359_DA_VSIM1_B_EN_ADDR MT6359_LDO_VSIM1_MON\n+#define MT6359_RG_LDO_VSIM2_EN_ADDR MT6359_LDO_VSIM2_CON0\n+#define MT6359_RG_LDO_VSIM2_EN_SHIFT 0\n+#define MT6359_DA_VSIM2_B_EN_ADDR MT6359_LDO_VSIM2_MON\n+#define MT6359_RG_LDO_VUSB_EN_0_ADDR MT6359_LDO_VUSB_CON0\n+#define MT6359_RG_LDO_VUSB_EN_0_MASK 0x1\n+#define MT6359_RG_LDO_VUSB_EN_0_SHIFT 0\n+#define MT6359_DA_VUSB_B_EN_ADDR MT6359_LDO_VUSB_MON\n+#define MT6359_RG_LDO_VUSB_EN_1_ADDR MT6359_LDO_VUSB_MULTI_SW\n+#define MT6359_RG_LDO_VUSB_EN_1_MASK 0x1\n+#define MT6359_RG_LDO_VUSB_EN_1_SHIFT 15\n+#define MT6359_RG_LDO_VRFCK_EN_ADDR MT6359_LDO_VRFCK_CON0\n+#define MT6359_RG_LDO_VRFCK_EN_SHIFT 0\n+#define MT6359_DA_VRFCK_B_EN_ADDR MT6359_LDO_VRFCK_MON\n+#define MT6359_RG_LDO_VBBCK_EN_ADDR MT6359_LDO_VBBCK_CON0\n+#define MT6359_RG_LDO_VBBCK_EN_SHIFT 0\n+#define MT6359_DA_VBBCK_B_EN_ADDR MT6359_LDO_VBBCK_MON\n+#define MT6359_RG_LDO_VBIF28_EN_ADDR MT6359_LDO_VBIF28_CON0\n+#define MT6359_DA_VBIF28_B_EN_ADDR MT6359_LDO_VBIF28_MON\n+#define MT6359_RG_LDO_VIBR_EN_ADDR MT6359_LDO_VIBR_CON0\n+#define MT6359_RG_LDO_VIBR_EN_SHIFT 0\n+#define MT6359_DA_VIBR_B_EN_ADDR MT6359_LDO_VIBR_MON\n+#define MT6359_RG_LDO_VIO28_EN_ADDR MT6359_LDO_VIO28_CON0\n+#define MT6359_RG_LDO_VIO28_EN_SHIFT 0\n+#define MT6359_DA_VIO28_B_EN_ADDR MT6359_LDO_VIO28_MON\n+#define MT6359_RG_LDO_VM18_EN_ADDR MT6359_LDO_VM18_CON0\n+#define MT6359_RG_LDO_VM18_EN_SHIFT 0\n+#define MT6359_DA_VM18_B_EN_ADDR MT6359_LDO_VM18_MON\n+#define MT6359_RG_LDO_VUFS_EN_ADDR MT6359_LDO_VUFS_CON0\n+#define MT6359_RG_LDO_VUFS_EN_SHIFT 0\n+#define MT6359_DA_VUFS_B_EN_ADDR MT6359_LDO_VUFS_MON\n+#define MT6359_RG_LDO_VSRAM_PROC1_EN_ADDR MT6359_LDO_VSRAM_PROC1_CON0\n+#define MT6359_DA_VSRAM_PROC1_B_EN_ADDR MT6359_LDO_VSRAM_PROC1_MON\n+#define MT6359_DA_VSRAM_PROC1_VOSEL_ADDR MT6359_LDO_VSRAM_PROC1_VOSEL1\n+#define MT6359_DA_VSRAM_PROC1_VOSEL_MASK 0x7F\n+#define MT6359_DA_VSRAM_PROC1_VOSEL_SHIFT 8\n+#define MT6359_RG_LDO_VSRAM_PROC2_EN_ADDR MT6359_LDO_VSRAM_PROC2_CON0\n+#define MT6359_DA_VSRAM_PROC2_B_EN_ADDR MT6359_LDO_VSRAM_PROC2_MON\n+#define MT6359_DA_VSRAM_PROC2_VOSEL_ADDR MT6359_LDO_VSRAM_PROC2_VOSEL1\n+#define MT6359_DA_VSRAM_PROC2_VOSEL_MASK 0x7F\n+#define MT6359_DA_VSRAM_PROC2_VOSEL_SHIFT 8\n+#define MT6359_RG_LDO_VSRAM_OTHERS_EN_ADDR MT6359_LDO_VSRAM_OTHERS_CON0\n+#define MT6359_DA_VSRAM_OTHERS_B_EN_ADDR MT6359_LDO_VSRAM_OTHERS_MON\n+#define MT6359_DA_VSRAM_OTHERS_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_VOSEL1\n+#define MT6359_DA_VSRAM_OTHERS_VOSEL_MASK 0x7F\n+#define MT6359_DA_VSRAM_OTHERS_VOSEL_SHIFT 8\n+#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR MT6359_LDO_VSRAM_OTHERS_SSHUB\n+#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR MT6359_LDO_VSRAM_OTHERS_SSHUB\n+#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK 0x7F\n+#define MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT 1\n+#define MT6359_RG_LDO_VSRAM_MD_EN_ADDR MT6359_LDO_VSRAM_MD_CON0\n+#define MT6359_DA_VSRAM_MD_B_EN_ADDR MT6359_LDO_VSRAM_MD_MON\n+#define MT6359_DA_VSRAM_MD_VOSEL_ADDR MT6359_LDO_VSRAM_MD_VOSEL1\n+#define MT6359_DA_VSRAM_MD_VOSEL_MASK 0x7F\n+#define MT6359_DA_VSRAM_MD_VOSEL_SHIFT 8\n+#define MT6359_RG_VCN33_1_VOSEL_ADDR MT6359_VCN33_1_ANA_CON0\n+#define MT6359_RG_VCN33_1_VOSEL_MASK 0xF\n+#define MT6359_RG_VCN33_1_VOSEL_SHIFT 8\n+#define MT6359_RG_VCN33_2_VOSEL_ADDR MT6359_VCN33_2_ANA_CON0\n+#define MT6359_RG_VCN33_2_VOSEL_MASK 0xF\n+#define MT6359_RG_VCN33_2_VOSEL_SHIFT 8\n+#define MT6359_RG_VEMC_VOSEL_ADDR MT6359_VEMC_ANA_CON0\n+#define MT6359_RG_VEMC_VOSEL_MASK 0xF\n+#define MT6359_RG_VEMC_VOSEL_SHIFT 8\n+#define MT6359_RG_VSIM1_VOSEL_ADDR MT6359_VSIM1_ANA_CON0\n+#define MT6359_RG_VSIM1_VOSEL_MASK 0xF\n+#define MT6359_RG_VSIM1_VOSEL_SHIFT 8\n+#define MT6359_RG_VSIM2_VOSEL_ADDR MT6359_VSIM2_ANA_CON0\n+#define MT6359_RG_VSIM2_VOSEL_MASK 0xF\n+#define MT6359_RG_VSIM2_VOSEL_SHIFT 8\n+#define MT6359_RG_VIO28_VOSEL_ADDR MT6359_VIO28_ANA_CON0\n+#define MT6359_RG_VIO28_VOSEL_MASK 0xF\n+#define MT6359_RG_VIO28_VOSEL_SHIFT 8\n+#define MT6359_RG_VIBR_VOSEL_ADDR MT6359_VIBR_ANA_CON0\n+#define MT6359_RG_VIBR_VOSEL_MASK 0xF\n+#define MT6359_RG_VIBR_VOSEL_SHIFT 8\n+#define MT6359_RG_VRF18_VOSEL_ADDR MT6359_VRF18_ANA_CON0\n+#define MT6359_RG_VRF18_VOSEL_MASK 0xF\n+#define MT6359_RG_VRF18_VOSEL_SHIFT 8\n+#define MT6359_RG_VEFUSE_VOSEL_ADDR MT6359_VEFUSE_ANA_CON0\n+#define MT6359_RG_VEFUSE_VOSEL_MASK 0xF\n+#define MT6359_RG_VEFUSE_VOSEL_SHIFT 8\n+#define MT6359_RG_VCAMIO_VOSEL_ADDR MT6359_VCAMIO_ANA_CON0\n+#define MT6359_RG_VCAMIO_VOSEL_MASK 0xF\n+#define MT6359_RG_VCAMIO_VOSEL_SHIFT 8\n+#define MT6359_RG_VIO18_VOSEL_ADDR MT6359_VIO18_ANA_CON0\n+#define MT6359_RG_VIO18_VOSEL_MASK 0xF\n+#define MT6359_RG_VIO18_VOSEL_SHIFT 8\n+#define MT6359_RG_VM18_VOSEL_ADDR MT6359_VM18_ANA_CON0\n+#define MT6359_RG_VM18_VOSEL_MASK 0xF\n+#define MT6359_RG_VM18_VOSEL_SHIFT 8\n+#define MT6359_RG_VUFS_VOSEL_ADDR MT6359_VUFS_ANA_CON0\n+#define MT6359_RG_VUFS_VOSEL_MASK 0xF\n+#define MT6359_RG_VUFS_VOSEL_SHIFT 8\n+#define MT6359_RG_VRF12_VOSEL_ADDR MT6359_VRF12_ANA_CON0\n+#define MT6359_RG_VRF12_VOSEL_MASK 0xF\n+#define MT6359_RG_VRF12_VOSEL_SHIFT 8\n+#define MT6359_RG_VCN13_VOSEL_ADDR MT6359_VCN13_ANA_CON0\n+#define MT6359_RG_VCN13_VOSEL_MASK 0xF\n+#define MT6359_RG_VCN13_VOSEL_SHIFT 8\n+#define MT6359_RG_VA09_VOSEL_ADDR MT6359_VA09_ANA_CON0\n+#define MT6359_RG_VA09_VOSEL_MASK 0xF\n+#define MT6359_RG_VA09_VOSEL_SHIFT 8\n+#define MT6359_RG_VA12_VOSEL_ADDR MT6359_VA12_ANA_CON0\n+#define MT6359_RG_VA12_VOSEL_MASK 0xF\n+#define MT6359_RG_VA12_VOSEL_SHIFT 8\n+#define MT6359_RG_VXO22_VOSEL_ADDR MT6359_VXO22_ANA_CON0\n+#define MT6359_RG_VXO22_VOSEL_MASK 0xF\n+#define MT6359_RG_VXO22_VOSEL_SHIFT 8\n+#define MT6359_RG_VRFCK_VOSEL_ADDR MT6359_VRFCK_ANA_CON0\n+#define MT6359_RG_VRFCK_VOSEL_MASK 0xF\n+#define MT6359_RG_VRFCK_VOSEL_SHIFT 8\n+#define MT6359_RG_VBBCK_VOSEL_ADDR MT6359_VBBCK_ANA_CON0\n+#define MT6359_RG_VBBCK_VOSEL_MASK 0xF\n+#define MT6359_RG_VBBCK_VOSEL_SHIFT 8\n+\n+#endif /* __MFD_MT6359_REGISTERS_H__ */\ndiff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h\nindex 9492685..56f210e 100644\n--- a/include/linux/mfd/mt6397/core.h\n+++ b/include/linux/mfd/mt6397/core.h\n@@ -13,6 +13,7 @@\n enum chip_id {\n \tMT6323_CHIP_ID = 0x23,\n \tMT6358_CHIP_ID = 0x58,\n+\tMT6359_CHIP_ID = 0x59,\n \tMT6391_CHIP_ID = 0x91,\n \tMT6397_CHIP_ID = 0x97,\n };\n", "prefixes": [ "v8", "5/8" ] }