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GET /api/patches/1267789/?format=api
{ "id": 1267789, "url": "http://patchwork.ozlabs.org/api/patches/1267789/?format=api", "web_url": "http://patchwork.ozlabs.org/project/rtc-linux/patch/1586333531-21641-5-git-send-email-hsin-hsiung.wang@mediatek.com/", "project": { "id": 9, "url": "http://patchwork.ozlabs.org/api/projects/9/?format=api", "name": "Linux RTC development", "link_name": "rtc-linux", "list_id": "linux-rtc.vger.kernel.org", "list_email": "linux-rtc@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1586333531-21641-5-git-send-email-hsin-hsiung.wang@mediatek.com>", "list_archive_url": null, "date": "2020-04-08T08:12:09", "name": "[v12,4/6] mfd: Add support for the MediaTek MT6358 PMIC", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": false, "hash": "fef89df828c7afc4a62db81abd017e81ab9fdb77", "submitter": { "id": 74946, "url": "http://patchwork.ozlabs.org/api/people/74946/?format=api", "name": "Hsin-Hsiung Wang", "email": "hsin-hsiung.wang@mediatek.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/rtc-linux/patch/1586333531-21641-5-git-send-email-hsin-hsiung.wang@mediatek.com/mbox/", "series": [ { "id": 169156, "url": "http://patchwork.ozlabs.org/api/series/169156/?format=api", "web_url": "http://patchwork.ozlabs.org/project/rtc-linux/list/?series=169156", "date": "2020-04-08T08:12:06", "name": "Add Support for MediaTek PMIC MT6358", "version": 12, "mbox": "http://patchwork.ozlabs.org/series/169156/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1267789/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1267789/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-rtc-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org; spf=none (no SPF record)\n\tsmtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67;\n\thelo=vger.kernel.org;\n\tenvelope-from=linux-rtc-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=pass (p=none dis=none)\n\theader.from=mediatek.com", "ozlabs.org; dkim=pass (1024-bit key;\n\tunprotected) header.d=mediatek.com header.i=@mediatek.com\n\theader.a=rsa-sha256 header.s=dk header.b=h/nf+Alx; \n\tdkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 48xxqR6WWTz9sSv\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 8 Apr 2020 18:13:23 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1726345AbgDHINR (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tWed, 8 Apr 2020 04:13:17 -0400", "from mailgw01.mediatek.com ([210.61.82.183]:47442 \"EHLO\n\tmailgw01.mediatek.com\" rhost-flags-OK-FAIL-OK-FAIL) by\n\tvger.kernel.org with ESMTP id S1727193AbgDHINQ (ORCPT\n\t<rfc822;linux-rtc@vger.kernel.org>); Wed, 8 Apr 2020 04:13:16 -0400", "from mtkcas11.mediatek.inc [(172.21.101.40)] by\n\tmailgw01.mediatek.com\n\t(envelope-from <hsin-hsiung.wang@mediatek.com>)\n\t(Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS)\n\twith ESMTP id 352671276; Wed, 08 Apr 2020 16:12:53 +0800", "from MTKCAS06.mediatek.inc (172.21.101.30) by\n\tmtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server\n\t(TLS) id 15.0.1497.2; Wed, 8 Apr 2020 16:12:49 +0800", "from mtksdaap41.mediatek.inc (172.21.77.4) by MTKCAS06.mediatek.inc\n\t(172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via\n\tFrontend Transport; Wed, 8 Apr 2020 16:12:49 +0800" ], "X-UUID": [ "b446631f8650437291e7f3b698f3e8f5-20200408", "b446631f8650437291e7f3b698f3e8f5-20200408" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=mediatek.com; s=dk; \n\th=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From;\n\tbh=XxTt5hTWupsouEgw7HVbvyrWfFH9r//ol77SKiDkxzE=; \n\tb=h/nf+Alx+kR/WY4AOYxBvFCxUNTEZzbUCcg1NctVf1fSKmry+eNZTc75BiIQpk5vYCsF8uK5sYwNkkOJXOASvJ7MGRTccWF2xcnYdbB/WibpAZcYcNVEzu+av/Bj438TQ5ME9la4/vj8eghxhejQWJEkLwwwszUmMQjKT40UiGc=;", "From": "Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>", "To": "Lee Jones <lee.jones@linaro.org>, Rob Herring <robh+dt@kernel.org>,\n\tMatthias Brugger <matthias.bgg@gmail.com>,\n\tAlexandre Belloni <alexandre.belloni@bootlin.com>", "CC": "Nicolas Boichat <drinkcat@chromium.org>,\n\tMark Rutland <mark.rutland@arm.com>, Sean Wang <sean.wang@mediatek.com>,\n\tSebastian Reichel <sre@kernel.org>,\n\tEddie Huang <eddie.huang@mediatek.com>,\n\tAlessandro Zummo <a.zummo@towertech.it>,\n\tKate Stewart <kstewart@linuxfoundation.org>,\n\tRichard Fontana <rfontana@redhat.com>,\n\tFrank Wunderlich <frank-w@public-files.de>,\n\tJosef Friedl <josef.friedl@speed.at>,\n\tThomas Gleixner <tglx@linutronix.de>,\n\tHsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>,\n\tRan Bi <ran.bi@mediatek.com>, <devicetree@vger.kernel.org>,\n\t<linux-arm-kernel@lists.infradead.org>,\n\t<linux-mediatek@lists.infradead.org>,\n\t<linux-kernel@vger.kernel.org>, <linux-pm@vger.kernel.org>,\n\t<linux-rtc@vger.kernel.org>, <srv_heupstream@mediatek.com>", "Subject": "[PATCH v12 4/6] mfd: Add support for the MediaTek MT6358 PMIC", "Date": "Wed, 8 Apr 2020 16:12:09 +0800", "Message-ID": "<1586333531-21641-5-git-send-email-hsin-hsiung.wang@mediatek.com>", "X-Mailer": "git-send-email 2.6.4", "In-Reply-To": "<1586333531-21641-1-git-send-email-hsin-hsiung.wang@mediatek.com>", "References": "<1586333531-21641-1-git-send-email-hsin-hsiung.wang@mediatek.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-MTK": "N", "Content-Transfer-Encoding": "base64", "Sender": "linux-rtc-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-rtc.vger.kernel.org>", "X-Mailing-List": "linux-rtc@vger.kernel.org" }, "content": "This adds support for the MediaTek MT6358 PMIC. This is a\nmultifunction device with the following sub modules:\n\n- Regulator\n- RTC\n- Codec\n- Interrupt\n\nIt is interfaced to the host controller using SPI interface\nby a proprietary hardware called PMIC wrapper or pwrap.\nMT6358 MFD is a child device of the pwrap.\n\nSigned-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>\n---\n drivers/mfd/Makefile | 2 +-\n drivers/mfd/mt6358-irq.c | 235 +++++++++++++++++++++++++++++\n drivers/mfd/mt6397-core.c | 36 +++++\n include/linux/mfd/mt6358/core.h | 158 ++++++++++++++++++++\n include/linux/mfd/mt6358/registers.h | 282 +++++++++++++++++++++++++++++++++++\n include/linux/mfd/mt6397/core.h | 3 +\n 6 files changed, 715 insertions(+), 1 deletion(-)\n create mode 100644 drivers/mfd/mt6358-irq.c\n create mode 100644 include/linux/mfd/mt6358/core.h\n create mode 100644 include/linux/mfd/mt6358/registers.h", "diff": "diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile\r\nindex b83f172..9af1414 100644\r\n--- a/drivers/mfd/Makefile\r\n+++ b/drivers/mfd/Makefile\r\n@@ -238,7 +238,7 @@ obj-$(CONFIG_INTEL_SOC_PMIC)\t+= intel-soc-pmic.o\r\n obj-$(CONFIG_INTEL_SOC_PMIC_BXTWC)\t+= intel_soc_pmic_bxtwc.o\r\n obj-$(CONFIG_INTEL_SOC_PMIC_CHTWC)\t+= intel_soc_pmic_chtwc.o\r\n obj-$(CONFIG_INTEL_SOC_PMIC_CHTDC_TI)\t+= intel_soc_pmic_chtdc_ti.o\r\n-mt6397-objs\t:= mt6397-core.o mt6397-irq.o\r\n+mt6397-objs\t\t\t:= mt6397-core.o mt6397-irq.o mt6358-irq.o\r\n obj-$(CONFIG_MFD_MT6397)\t+= mt6397.o\r\n obj-$(CONFIG_INTEL_SOC_PMIC_MRFLD)\t+= intel_soc_pmic_mrfld.o\r\n \r\ndiff --git a/drivers/mfd/mt6358-irq.c b/drivers/mfd/mt6358-irq.c\r\nnew file mode 100644\r\nindex 0000000..db734f2\r\n--- /dev/null\r\n+++ b/drivers/mfd/mt6358-irq.c\r\n@@ -0,0 +1,235 @@\r\n+// SPDX-License-Identifier: GPL-2.0\r\n+//\r\n+// Copyright (c) 2020 MediaTek Inc.\r\n+\r\n+#include <linux/interrupt.h>\r\n+#include <linux/mfd/mt6358/core.h>\r\n+#include <linux/mfd/mt6358/registers.h>\r\n+#include <linux/mfd/mt6397/core.h>\r\n+#include <linux/module.h>\r\n+#include <linux/of.h>\r\n+#include <linux/of_device.h>\r\n+#include <linux/of_irq.h>\r\n+#include <linux/platform_device.h>\r\n+#include <linux/regmap.h>\r\n+\r\n+static struct irq_top_t mt6358_ints[] = {\r\n+\tMT6358_TOP_GEN(BUCK),\r\n+\tMT6358_TOP_GEN(LDO),\r\n+\tMT6358_TOP_GEN(PSC),\r\n+\tMT6358_TOP_GEN(SCK),\r\n+\tMT6358_TOP_GEN(BM),\r\n+\tMT6358_TOP_GEN(HK),\r\n+\tMT6358_TOP_GEN(AUD),\r\n+\tMT6358_TOP_GEN(MISC),\r\n+};\r\n+\r\n+static void pmic_irq_enable(struct irq_data *data)\r\n+{\r\n+\tunsigned int hwirq = irqd_to_hwirq(data);\r\n+\tstruct mt6397_chip *chip = irq_data_get_irq_chip_data(data);\r\n+\tstruct pmic_irq_data *irqd = chip->irq_data;\r\n+\r\n+\tirqd->enable_hwirq[hwirq] = true;\r\n+}\r\n+\r\n+static void pmic_irq_disable(struct irq_data *data)\r\n+{\r\n+\tunsigned int hwirq = irqd_to_hwirq(data);\r\n+\tstruct mt6397_chip *chip = irq_data_get_irq_chip_data(data);\r\n+\tstruct pmic_irq_data *irqd = chip->irq_data;\r\n+\r\n+\tirqd->enable_hwirq[hwirq] = false;\r\n+}\r\n+\r\n+static void pmic_irq_lock(struct irq_data *data)\r\n+{\r\n+\tstruct mt6397_chip *chip = irq_data_get_irq_chip_data(data);\r\n+\r\n+\tmutex_lock(&chip->irqlock);\r\n+}\r\n+\r\n+static void pmic_irq_sync_unlock(struct irq_data *data)\r\n+{\r\n+\tunsigned int i, top_gp, gp_offset, en_reg, int_regs, shift;\r\n+\tstruct mt6397_chip *chip = irq_data_get_irq_chip_data(data);\r\n+\tstruct pmic_irq_data *irqd = chip->irq_data;\r\n+\r\n+\tfor (i = 0; i < irqd->num_pmic_irqs; i++) {\r\n+\t\tif (irqd->enable_hwirq[i] == irqd->cache_hwirq[i])\r\n+\t\t\tcontinue;\r\n+\r\n+\t\t/* Find out the IRQ group */\r\n+\t\ttop_gp = 0;\r\n+\t\twhile ((top_gp + 1) < irqd->num_top &&\r\n+\t\t i >= mt6358_ints[top_gp + 1].hwirq_base)\r\n+\t\t\ttop_gp++;\r\n+\r\n+\t\t/* Find the IRQ registers */\r\n+\t\tgp_offset = i - mt6358_ints[top_gp].hwirq_base;\r\n+\t\tint_regs = gp_offset / MT6358_REG_WIDTH;\r\n+\t\tshift = gp_offset % MT6358_REG_WIDTH;\r\n+\t\ten_reg = mt6358_ints[top_gp].en_reg +\r\n+\t\t\t (mt6358_ints[top_gp].en_reg_shift * int_regs);\r\n+\r\n+\t\tregmap_update_bits(chip->regmap, en_reg, BIT(shift),\r\n+\t\t\t\t irqd->enable_hwirq[i] << shift);\r\n+\r\n+\t\tirqd->cache_hwirq[i] = irqd->enable_hwirq[i];\r\n+\t}\r\n+\tmutex_unlock(&chip->irqlock);\r\n+}\r\n+\r\n+static struct irq_chip mt6358_irq_chip = {\r\n+\t.name = \"mt6358-irq\",\r\n+\t.flags = IRQCHIP_SKIP_SET_WAKE,\r\n+\t.irq_enable = pmic_irq_enable,\r\n+\t.irq_disable = pmic_irq_disable,\r\n+\t.irq_bus_lock = pmic_irq_lock,\r\n+\t.irq_bus_sync_unlock = pmic_irq_sync_unlock,\r\n+};\r\n+\r\n+static void mt6358_irq_sp_handler(struct mt6397_chip *chip,\r\n+\t\t\t\t unsigned int top_gp)\r\n+{\r\n+\tunsigned int irq_status, sta_reg, status;\r\n+\tunsigned int hwirq, virq;\r\n+\tint i, j, ret;\r\n+\r\n+\tfor (i = 0; i < mt6358_ints[top_gp].num_int_regs; i++) {\r\n+\t\tsta_reg = mt6358_ints[top_gp].sta_reg +\r\n+\t\t\tmt6358_ints[top_gp].sta_reg_shift * i;\r\n+\r\n+\t\tret = regmap_read(chip->regmap, sta_reg, &irq_status);\r\n+\t\tif (ret) {\r\n+\t\t\tdev_err(chip->dev,\r\n+\t\t\t\t\"Failed to read IRQ status, ret=%d\\n\", ret);\r\n+\t\t\treturn;\r\n+\t\t}\r\n+\r\n+\t\tif (!irq_status)\r\n+\t\t\tcontinue;\r\n+\r\n+\t\tstatus = irq_status;\r\n+\t\tdo {\r\n+\t\t\tj = __ffs(status);\r\n+\r\n+\t\t\thwirq = mt6358_ints[top_gp].hwirq_base +\r\n+\t\t\t\tMT6358_REG_WIDTH * i + j;\r\n+\r\n+\t\t\tvirq = irq_find_mapping(chip->irq_domain, hwirq);\r\n+\t\t\tif (virq)\r\n+\t\t\t\thandle_nested_irq(virq);\r\n+\r\n+\t\t\tstatus &= ~BIT(j);\r\n+\t\t} while (status);\r\n+\r\n+\t\tregmap_write(chip->regmap, sta_reg, irq_status);\r\n+\t}\r\n+}\r\n+\r\n+static irqreturn_t mt6358_irq_handler(int irq, void *data)\r\n+{\r\n+\tstruct mt6397_chip *chip = data;\r\n+\tstruct pmic_irq_data *mt6358_irq_data = chip->irq_data;\r\n+\tunsigned int bit, i, top_irq_status = 0;\r\n+\tint ret;\r\n+\r\n+\tret = regmap_read(chip->regmap,\r\n+\t\t\t mt6358_irq_data->top_int_status_reg,\r\n+\t\t\t &top_irq_status);\r\n+\tif (ret) {\r\n+\t\tdev_err(chip->dev,\r\n+\t\t\t\"Failed to read status from the device, ret=%d\\n\", ret);\r\n+\t\treturn IRQ_NONE;\r\n+\t}\r\n+\r\n+\tfor (i = 0; i < mt6358_irq_data->num_top; i++) {\r\n+\t\tbit = BIT(mt6358_ints[i].top_offset);\r\n+\t\tif (top_irq_status & bit) {\r\n+\t\t\tmt6358_irq_sp_handler(chip, i);\r\n+\t\t\ttop_irq_status &= ~bit;\r\n+\t\t\tif (!top_irq_status)\r\n+\t\t\t\tbreak;\r\n+\t\t}\r\n+\t}\r\n+\r\n+\treturn IRQ_HANDLED;\r\n+}\r\n+\r\n+static int pmic_irq_domain_map(struct irq_domain *d, unsigned int irq,\r\n+\t\t\t irq_hw_number_t hw)\r\n+{\r\n+\tstruct mt6397_chip *mt6397 = d->host_data;\r\n+\r\n+\tirq_set_chip_data(irq, mt6397);\r\n+\tirq_set_chip_and_handler(irq, &mt6358_irq_chip, handle_level_irq);\r\n+\tirq_set_nested_thread(irq, 1);\r\n+\tirq_set_noprobe(irq);\r\n+\r\n+\treturn 0;\r\n+}\r\n+\r\n+static const struct irq_domain_ops mt6358_irq_domain_ops = {\r\n+\t.map = pmic_irq_domain_map,\r\n+\t.xlate = irq_domain_xlate_twocell,\r\n+};\r\n+\r\n+int mt6358_irq_init(struct mt6397_chip *chip)\r\n+{\r\n+\tint i, j, ret;\r\n+\tstruct pmic_irq_data *irqd;\r\n+\r\n+\tirqd = devm_kzalloc(chip->dev, sizeof(*irqd), GFP_KERNEL);\r\n+\tif (!irqd)\r\n+\t\treturn -ENOMEM;\r\n+\r\n+\tchip->irq_data = irqd;\r\n+\r\n+\tmutex_init(&chip->irqlock);\r\n+\tirqd->top_int_status_reg = MT6358_TOP_INT_STATUS0;\r\n+\tirqd->num_pmic_irqs = MT6358_IRQ_NR;\r\n+\tirqd->num_top = ARRAY_SIZE(mt6358_ints);\r\n+\r\n+\tirqd->enable_hwirq = devm_kcalloc(chip->dev,\r\n+\t\t\t\t\t irqd->num_pmic_irqs,\r\n+\t\t\t\t\t sizeof(*irqd->enable_hwirq),\r\n+\t\t\t\t\t GFP_KERNEL);\r\n+\tif (!irqd->enable_hwirq)\r\n+\t\treturn -ENOMEM;\r\n+\r\n+\tirqd->cache_hwirq = devm_kcalloc(chip->dev,\r\n+\t\t\t\t\t irqd->num_pmic_irqs,\r\n+\t\t\t\t\t sizeof(*irqd->cache_hwirq),\r\n+\t\t\t\t\t GFP_KERNEL);\r\n+\tif (!irqd->cache_hwirq)\r\n+\t\treturn -ENOMEM;\r\n+\r\n+\t/* Disable all interrupts for initializing */\r\n+\tfor (i = 0; i < irqd->num_top; i++) {\r\n+\t\tfor (j = 0; j < mt6358_ints[i].num_int_regs; j++)\r\n+\t\t\tregmap_write(chip->regmap,\r\n+\t\t\t\t mt6358_ints[i].en_reg +\r\n+\t\t\t\t mt6358_ints[i].en_reg_shift * j, 0);\r\n+\t}\r\n+\r\n+\tchip->irq_domain = irq_domain_add_linear(chip->dev->of_node,\r\n+\t\t\t\t\t\t irqd->num_pmic_irqs,\r\n+\t\t\t\t\t\t &mt6358_irq_domain_ops, chip);\r\n+\tif (!chip->irq_domain) {\r\n+\t\tdev_err(chip->dev, \"Could not create IRQ domain\\n\");\r\n+\t\treturn -ENODEV;\r\n+\t}\r\n+\r\n+\tret = devm_request_threaded_irq(chip->dev, chip->irq, NULL,\r\n+\t\t\t\t\tmt6358_irq_handler, IRQF_ONESHOT,\r\n+\t\t\t\t\tmt6358_irq_chip.name, chip);\r\n+\tif (ret) {\r\n+\t\tdev_err(chip->dev, \"Failed to register IRQ=%d, ret=%d\\n\",\r\n+\t\t\tchip->irq, ret);\r\n+\t\treturn ret;\r\n+\t}\r\n+\r\n+\tenable_irq_wake(chip->irq);\r\n+\treturn ret;\r\n+}\r\ndiff --git a/drivers/mfd/mt6397-core.c b/drivers/mfd/mt6397-core.c\r\nindex a313a72..f6cd8a6 100644\r\n--- a/drivers/mfd/mt6397-core.c\r\n+++ b/drivers/mfd/mt6397-core.c\r\n@@ -12,13 +12,18 @@\r\n #include <linux/regmap.h>\r\n #include <linux/mfd/core.h>\r\n #include <linux/mfd/mt6323/core.h>\r\n+#include <linux/mfd/mt6358/core.h>\r\n #include <linux/mfd/mt6397/core.h>\r\n #include <linux/mfd/mt6323/registers.h>\r\n+#include <linux/mfd/mt6358/registers.h>\r\n #include <linux/mfd/mt6397/registers.h>\r\n \r\n #define MT6323_RTC_BASE\t\t0x8000\r\n #define MT6323_RTC_SIZE\t\t0x40\r\n \r\n+#define MT6358_RTC_BASE\t\t0x0588\r\n+#define MT6358_RTC_SIZE\t\t0x3c\r\n+\r\n #define MT6397_RTC_BASE\t\t0xe000\r\n #define MT6397_RTC_SIZE\t\t0x3e\r\n \r\n@@ -30,6 +35,11 @@ static const struct resource mt6323_rtc_resources[] = {\r\n \tDEFINE_RES_IRQ(MT6323_IRQ_STATUS_RTC),\r\n };\r\n \r\n+static const struct resource mt6358_rtc_resources[] = {\r\n+\tDEFINE_RES_MEM(MT6358_RTC_BASE, MT6358_RTC_SIZE),\r\n+\tDEFINE_RES_IRQ(MT6358_IRQ_RTC),\r\n+};\r\n+\r\n static const struct resource mt6397_rtc_resources[] = {\r\n \tDEFINE_RES_MEM(MT6397_RTC_BASE, MT6397_RTC_SIZE),\r\n \tDEFINE_RES_IRQ(MT6397_IRQ_RTC),\r\n@@ -74,6 +84,21 @@ static const struct mfd_cell mt6323_devs[] = {\r\n \t},\r\n };\r\n \r\n+static const struct mfd_cell mt6358_devs[] = {\r\n+\t{\r\n+\t\t.name = \"mt6358-regulator\",\r\n+\t\t.of_compatible = \"mediatek,mt6358-regulator\"\r\n+\t}, {\r\n+\t\t.name = \"mt6358-rtc\",\r\n+\t\t.num_resources = ARRAY_SIZE(mt6358_rtc_resources),\r\n+\t\t.resources = mt6358_rtc_resources,\r\n+\t\t.of_compatible = \"mediatek,mt6358-rtc\",\r\n+\t}, {\r\n+\t\t.name = \"mt6358-sound\",\r\n+\t\t.of_compatible = \"mediatek,mt6358-sound\"\r\n+\t},\r\n+};\r\n+\r\n static const struct mfd_cell mt6397_devs[] = {\r\n \t{\r\n \t\t.name = \"mt6397-rtc\",\r\n@@ -116,6 +141,14 @@ static const struct chip_data mt6323_core = {\r\n \t.irq_init = mt6397_irq_init,\r\n };\r\n \r\n+static const struct chip_data mt6358_core = {\r\n+\t.cid_addr = MT6358_SWCID,\r\n+\t.cid_shift = 8,\r\n+\t.cells = mt6358_devs,\r\n+\t.cell_size = ARRAY_SIZE(mt6358_devs),\r\n+\t.irq_init = mt6358_irq_init,\r\n+};\r\n+\r\n static const struct chip_data mt6397_core = {\r\n \t.cid_addr = MT6397_CID,\r\n \t.cid_shift = 0,\r\n@@ -183,6 +216,9 @@ static const struct of_device_id mt6397_of_match[] = {\r\n \t\t.compatible = \"mediatek,mt6323\",\r\n \t\t.data = &mt6323_core,\r\n \t}, {\r\n+\t\t.compatible = \"mediatek,mt6358\",\r\n+\t\t.data = &mt6358_core,\r\n+\t}, {\r\n \t\t.compatible = \"mediatek,mt6397\",\r\n \t\t.data = &mt6397_core,\r\n \t}, {\r\ndiff --git a/include/linux/mfd/mt6358/core.h b/include/linux/mfd/mt6358/core.h\r\nnew file mode 100644\r\nindex 0000000..a304aae\r\n--- /dev/null\r\n+++ b/include/linux/mfd/mt6358/core.h\r\n@@ -0,0 +1,158 @@\r\n+/* SPDX-License-Identifier: GPL-2.0 */\r\n+/*\r\n+ * Copyright (c) 2019 MediaTek Inc.\r\n+ */\r\n+\r\n+#ifndef __MFD_MT6358_CORE_H__\r\n+#define __MFD_MT6358_CORE_H__\r\n+\r\n+#define MT6358_REG_WIDTH 16\r\n+\r\n+struct irq_top_t {\r\n+\tint hwirq_base;\r\n+\tunsigned int num_int_regs;\r\n+\tunsigned int num_int_bits;\r\n+\tunsigned int en_reg;\r\n+\tunsigned int en_reg_shift;\r\n+\tunsigned int sta_reg;\r\n+\tunsigned int sta_reg_shift;\r\n+\tunsigned int top_offset;\r\n+};\r\n+\r\n+struct pmic_irq_data {\r\n+\tunsigned int num_top;\r\n+\tunsigned int num_pmic_irqs;\r\n+\tunsigned short top_int_status_reg;\r\n+\tbool *enable_hwirq;\r\n+\tbool *cache_hwirq;\r\n+};\r\n+\r\n+enum mt6358_irq_top_status_shift {\r\n+\tMT6358_BUCK_TOP = 0,\r\n+\tMT6358_LDO_TOP,\r\n+\tMT6358_PSC_TOP,\r\n+\tMT6358_SCK_TOP,\r\n+\tMT6358_BM_TOP,\r\n+\tMT6358_HK_TOP,\r\n+\tMT6358_AUD_TOP,\r\n+\tMT6358_MISC_TOP,\r\n+};\r\n+\r\n+enum mt6358_irq_numbers {\r\n+\tMT6358_IRQ_VPROC11_OC = 0,\r\n+\tMT6358_IRQ_VPROC12_OC,\r\n+\tMT6358_IRQ_VCORE_OC,\r\n+\tMT6358_IRQ_VGPU_OC,\r\n+\tMT6358_IRQ_VMODEM_OC,\r\n+\tMT6358_IRQ_VDRAM1_OC,\r\n+\tMT6358_IRQ_VS1_OC,\r\n+\tMT6358_IRQ_VS2_OC,\r\n+\tMT6358_IRQ_VPA_OC,\r\n+\tMT6358_IRQ_VCORE_PREOC,\r\n+\tMT6358_IRQ_VFE28_OC = 16,\r\n+\tMT6358_IRQ_VXO22_OC,\r\n+\tMT6358_IRQ_VRF18_OC,\r\n+\tMT6358_IRQ_VRF12_OC,\r\n+\tMT6358_IRQ_VEFUSE_OC,\r\n+\tMT6358_IRQ_VCN33_OC,\r\n+\tMT6358_IRQ_VCN28_OC,\r\n+\tMT6358_IRQ_VCN18_OC,\r\n+\tMT6358_IRQ_VCAMA1_OC,\r\n+\tMT6358_IRQ_VCAMA2_OC,\r\n+\tMT6358_IRQ_VCAMD_OC,\r\n+\tMT6358_IRQ_VCAMIO_OC,\r\n+\tMT6358_IRQ_VLDO28_OC,\r\n+\tMT6358_IRQ_VA12_OC,\r\n+\tMT6358_IRQ_VAUX18_OC,\r\n+\tMT6358_IRQ_VAUD28_OC,\r\n+\tMT6358_IRQ_VIO28_OC,\r\n+\tMT6358_IRQ_VIO18_OC,\r\n+\tMT6358_IRQ_VSRAM_PROC11_OC,\r\n+\tMT6358_IRQ_VSRAM_PROC12_OC,\r\n+\tMT6358_IRQ_VSRAM_OTHERS_OC,\r\n+\tMT6358_IRQ_VSRAM_GPU_OC,\r\n+\tMT6358_IRQ_VDRAM2_OC,\r\n+\tMT6358_IRQ_VMC_OC,\r\n+\tMT6358_IRQ_VMCH_OC,\r\n+\tMT6358_IRQ_VEMC_OC,\r\n+\tMT6358_IRQ_VSIM1_OC,\r\n+\tMT6358_IRQ_VSIM2_OC,\r\n+\tMT6358_IRQ_VIBR_OC,\r\n+\tMT6358_IRQ_VUSB_OC,\r\n+\tMT6358_IRQ_VBIF28_OC,\r\n+\tMT6358_IRQ_PWRKEY = 48,\r\n+\tMT6358_IRQ_HOMEKEY,\r\n+\tMT6358_IRQ_PWRKEY_R,\r\n+\tMT6358_IRQ_HOMEKEY_R,\r\n+\tMT6358_IRQ_NI_LBAT_INT,\r\n+\tMT6358_IRQ_CHRDET,\r\n+\tMT6358_IRQ_CHRDET_EDGE,\r\n+\tMT6358_IRQ_VCDT_HV_DET,\r\n+\tMT6358_IRQ_RTC = 64,\r\n+\tMT6358_IRQ_FG_BAT0_H = 80,\r\n+\tMT6358_IRQ_FG_BAT0_L,\r\n+\tMT6358_IRQ_FG_CUR_H,\r\n+\tMT6358_IRQ_FG_CUR_L,\r\n+\tMT6358_IRQ_FG_ZCV,\r\n+\tMT6358_IRQ_FG_BAT1_H,\r\n+\tMT6358_IRQ_FG_BAT1_L,\r\n+\tMT6358_IRQ_FG_N_CHARGE_L,\r\n+\tMT6358_IRQ_FG_IAVG_H,\r\n+\tMT6358_IRQ_FG_IAVG_L,\r\n+\tMT6358_IRQ_FG_TIME_H,\r\n+\tMT6358_IRQ_FG_DISCHARGE,\r\n+\tMT6358_IRQ_FG_CHARGE,\r\n+\tMT6358_IRQ_BATON_LV = 96,\r\n+\tMT6358_IRQ_BATON_HT,\r\n+\tMT6358_IRQ_BATON_BAT_IN,\r\n+\tMT6358_IRQ_BATON_BAT_OUT,\r\n+\tMT6358_IRQ_BIF,\r\n+\tMT6358_IRQ_BAT_H = 112,\r\n+\tMT6358_IRQ_BAT_L,\r\n+\tMT6358_IRQ_BAT2_H,\r\n+\tMT6358_IRQ_BAT2_L,\r\n+\tMT6358_IRQ_BAT_TEMP_H,\r\n+\tMT6358_IRQ_BAT_TEMP_L,\r\n+\tMT6358_IRQ_AUXADC_IMP,\r\n+\tMT6358_IRQ_NAG_C_DLTV,\r\n+\tMT6358_IRQ_AUDIO = 128,\r\n+\tMT6358_IRQ_ACCDET = 133,\r\n+\tMT6358_IRQ_ACCDET_EINT0,\r\n+\tMT6358_IRQ_ACCDET_EINT1,\r\n+\tMT6358_IRQ_SPI_CMD_ALERT = 144,\r\n+\tMT6358_IRQ_NR,\r\n+};\r\n+\r\n+#define MT6358_IRQ_BUCK_BASE MT6358_IRQ_VPROC11_OC\r\n+#define MT6358_IRQ_LDO_BASE MT6358_IRQ_VFE28_OC\r\n+#define MT6358_IRQ_PSC_BASE MT6358_IRQ_PWRKEY\r\n+#define MT6358_IRQ_SCK_BASE MT6358_IRQ_RTC\r\n+#define MT6358_IRQ_BM_BASE MT6358_IRQ_FG_BAT0_H\r\n+#define MT6358_IRQ_HK_BASE MT6358_IRQ_BAT_H\r\n+#define MT6358_IRQ_AUD_BASE MT6358_IRQ_AUDIO\r\n+#define MT6358_IRQ_MISC_BASE MT6358_IRQ_SPI_CMD_ALERT\r\n+\r\n+#define MT6358_IRQ_BUCK_BITS (MT6358_IRQ_VCORE_PREOC - MT6358_IRQ_BUCK_BASE + 1)\r\n+#define MT6358_IRQ_LDO_BITS (MT6358_IRQ_VBIF28_OC - MT6358_IRQ_LDO_BASE + 1)\r\n+#define MT6358_IRQ_PSC_BITS (MT6358_IRQ_VCDT_HV_DET - MT6358_IRQ_PSC_BASE + 1)\r\n+#define MT6358_IRQ_SCK_BITS (MT6358_IRQ_RTC - MT6358_IRQ_SCK_BASE + 1)\r\n+#define MT6358_IRQ_BM_BITS (MT6358_IRQ_BIF - MT6358_IRQ_BM_BASE + 1)\r\n+#define MT6358_IRQ_HK_BITS (MT6358_IRQ_NAG_C_DLTV - MT6358_IRQ_HK_BASE + 1)\r\n+#define MT6358_IRQ_AUD_BITS (MT6358_IRQ_ACCDET_EINT1 - MT6358_IRQ_AUD_BASE + 1)\r\n+#define MT6358_IRQ_MISC_BITS\t\\\r\n+\t(MT6358_IRQ_SPI_CMD_ALERT - MT6358_IRQ_MISC_BASE + 1)\r\n+\r\n+#define MT6358_TOP_GEN(sp)\t\\\r\n+{\t\\\r\n+\t.hwirq_base = MT6358_IRQ_##sp##_BASE,\t\\\r\n+\t.num_int_regs =\t\\\r\n+\t\t((MT6358_IRQ_##sp##_BITS - 1) / MT6358_REG_WIDTH) + 1,\t\\\r\n+\t.num_int_bits = MT6358_IRQ_##sp##_BITS, \\\r\n+\t.en_reg = MT6358_##sp##_TOP_INT_CON0,\t\\\r\n+\t.en_reg_shift = 0x6,\t\\\r\n+\t.sta_reg = MT6358_##sp##_TOP_INT_STATUS0,\t\\\r\n+\t.sta_reg_shift = 0x2,\t\\\r\n+\t.top_offset = MT6358_##sp##_TOP,\t\\\r\n+}\r\n+\r\n+#endif /* __MFD_MT6358_CORE_H__ */\r\ndiff --git a/include/linux/mfd/mt6358/registers.h b/include/linux/mfd/mt6358/registers.h\r\nnew file mode 100644\r\nindex 0000000..ff5645b\r\n--- /dev/null\r\n+++ b/include/linux/mfd/mt6358/registers.h\r\n@@ -0,0 +1,282 @@\r\n+/* SPDX-License-Identifier: GPL-2.0 */\r\n+/*\r\n+ * Copyright (c) 2019 MediaTek Inc.\r\n+ */\r\n+\r\n+#ifndef __MFD_MT6358_REGISTERS_H__\r\n+#define __MFD_MT6358_REGISTERS_H__\r\n+\r\n+/* PMIC Registers */\r\n+#define MT6358_SWCID 0xa\r\n+#define MT6358_MISC_TOP_INT_CON0 0x188\r\n+#define MT6358_MISC_TOP_INT_STATUS0 0x194\r\n+#define MT6358_TOP_INT_STATUS0 0x19e\r\n+#define MT6358_SCK_TOP_INT_CON0 0x52e\r\n+#define MT6358_SCK_TOP_INT_STATUS0 0x53a\r\n+#define MT6358_EOSC_CALI_CON0 0x540\r\n+#define MT6358_EOSC_CALI_CON1 0x542\r\n+#define MT6358_RTC_MIX_CON0 0x544\r\n+#define MT6358_RTC_MIX_CON1 0x546\r\n+#define MT6358_RTC_MIX_CON2 0x548\r\n+#define MT6358_RTC_DSN_ID 0x580\r\n+#define MT6358_RTC_DSN_REV0 0x582\r\n+#define MT6358_RTC_DBI 0x584\r\n+#define MT6358_RTC_DXI 0x586\r\n+#define MT6358_RTC_BBPU 0x588\r\n+#define MT6358_RTC_IRQ_STA 0x58a\r\n+#define MT6358_RTC_IRQ_EN 0x58c\r\n+#define MT6358_RTC_CII_EN 0x58e\r\n+#define MT6358_RTC_AL_MASK 0x590\r\n+#define MT6358_RTC_TC_SEC 0x592\r\n+#define MT6358_RTC_TC_MIN 0x594\r\n+#define MT6358_RTC_TC_HOU 0x596\r\n+#define MT6358_RTC_TC_DOM 0x598\r\n+#define MT6358_RTC_TC_DOW 0x59a\r\n+#define MT6358_RTC_TC_MTH 0x59c\r\n+#define MT6358_RTC_TC_YEA 0x59e\r\n+#define MT6358_RTC_AL_SEC 0x5a0\r\n+#define MT6358_RTC_AL_MIN 0x5a2\r\n+#define MT6358_RTC_AL_HOU 0x5a4\r\n+#define MT6358_RTC_AL_DOM 0x5a6\r\n+#define MT6358_RTC_AL_DOW 0x5a8\r\n+#define MT6358_RTC_AL_MTH 0x5aa\r\n+#define MT6358_RTC_AL_YEA 0x5ac\r\n+#define MT6358_RTC_OSC32CON 0x5ae\r\n+#define MT6358_RTC_POWERKEY1 0x5b0\r\n+#define MT6358_RTC_POWERKEY2 0x5b2\r\n+#define MT6358_RTC_PDN1 0x5b4\r\n+#define MT6358_RTC_PDN2 0x5b6\r\n+#define MT6358_RTC_SPAR0 0x5b8\r\n+#define MT6358_RTC_SPAR1 0x5ba\r\n+#define MT6358_RTC_PROT 0x5bc\r\n+#define MT6358_RTC_DIFF 0x5be\r\n+#define MT6358_RTC_CALI 0x5c0\r\n+#define MT6358_RTC_WRTGR 0x5c2\r\n+#define MT6358_RTC_CON 0x5c4\r\n+#define MT6358_RTC_SEC_CTRL 0x5c6\r\n+#define MT6358_RTC_INT_CNT 0x5c8\r\n+#define MT6358_RTC_SEC_DAT0 0x5ca\r\n+#define MT6358_RTC_SEC_DAT1 0x5cc\r\n+#define MT6358_RTC_SEC_DAT2 0x5ce\r\n+#define MT6358_RTC_SEC_DSN_ID 0x600\r\n+#define MT6358_RTC_SEC_DSN_REV0 0x602\r\n+#define MT6358_RTC_SEC_DBI 0x604\r\n+#define MT6358_RTC_SEC_DXI 0x606\r\n+#define MT6358_RTC_TC_SEC_SEC 0x608\r\n+#define MT6358_RTC_TC_MIN_SEC 0x60a\r\n+#define MT6358_RTC_TC_HOU_SEC 0x60c\r\n+#define MT6358_RTC_TC_DOM_SEC 0x60e\r\n+#define MT6358_RTC_TC_DOW_SEC 0x610\r\n+#define MT6358_RTC_TC_MTH_SEC 0x612\r\n+#define MT6358_RTC_TC_YEA_SEC 0x614\r\n+#define MT6358_RTC_SEC_CK_PDN 0x616\r\n+#define MT6358_RTC_SEC_WRTGR 0x618\r\n+#define MT6358_PSC_TOP_INT_CON0 0x910\r\n+#define MT6358_PSC_TOP_INT_STATUS0 0x91c\r\n+#define MT6358_BM_TOP_INT_CON0 0xc32\r\n+#define MT6358_BM_TOP_INT_CON1 0xc38\r\n+#define MT6358_BM_TOP_INT_STATUS0 0xc4a\r\n+#define MT6358_BM_TOP_INT_STATUS1 0xc4c\r\n+#define MT6358_HK_TOP_INT_CON0 0xf92\r\n+#define MT6358_HK_TOP_INT_STATUS0 0xf9e\r\n+#define MT6358_BUCK_TOP_INT_CON0 0x1318\r\n+#define MT6358_BUCK_TOP_INT_STATUS0 0x1324\r\n+#define MT6358_BUCK_VPROC11_CON0 0x1388\r\n+#define MT6358_BUCK_VPROC11_DBG0 0x139e\r\n+#define MT6358_BUCK_VPROC11_DBG1 0x13a0\r\n+#define MT6358_BUCK_VPROC11_ELR0 0x13a6\r\n+#define MT6358_BUCK_VPROC12_CON0 0x1408\r\n+#define MT6358_BUCK_VPROC12_DBG0 0x141e\r\n+#define MT6358_BUCK_VPROC12_DBG1 0x1420\r\n+#define MT6358_BUCK_VPROC12_ELR0 0x1426\r\n+#define MT6358_BUCK_VCORE_CON0 0x1488\r\n+#define MT6358_BUCK_VCORE_DBG0 0x149e\r\n+#define MT6358_BUCK_VCORE_DBG1 0x14a0\r\n+#define MT6358_BUCK_VCORE_ELR0 0x14aa\r\n+#define MT6358_BUCK_VGPU_CON0 0x1508\r\n+#define MT6358_BUCK_VGPU_DBG0 0x151e\r\n+#define MT6358_BUCK_VGPU_DBG1 0x1520\r\n+#define MT6358_BUCK_VGPU_ELR0 0x1526\r\n+#define MT6358_BUCK_VMODEM_CON0 0x1588\r\n+#define MT6358_BUCK_VMODEM_DBG0 0x159e\r\n+#define MT6358_BUCK_VMODEM_DBG1 0x15a0\r\n+#define MT6358_BUCK_VMODEM_ELR0 0x15a6\r\n+#define MT6358_BUCK_VDRAM1_CON0 0x1608\r\n+#define MT6358_BUCK_VDRAM1_DBG0 0x161e\r\n+#define MT6358_BUCK_VDRAM1_DBG1 0x1620\r\n+#define MT6358_BUCK_VDRAM1_ELR0 0x1626\r\n+#define MT6358_BUCK_VS1_CON0 0x1688\r\n+#define MT6358_BUCK_VS1_DBG0 0x169e\r\n+#define MT6358_BUCK_VS1_DBG1 0x16a0\r\n+#define MT6358_BUCK_VS1_ELR0 0x16ae\r\n+#define MT6358_BUCK_VS2_CON0 0x1708\r\n+#define MT6358_BUCK_VS2_DBG0 0x171e\r\n+#define MT6358_BUCK_VS2_DBG1 0x1720\r\n+#define MT6358_BUCK_VS2_ELR0 0x172e\r\n+#define MT6358_BUCK_VPA_CON0 0x1788\r\n+#define MT6358_BUCK_VPA_CON1 0x178a\r\n+#define MT6358_BUCK_VPA_ELR0 MT6358_BUCK_VPA_CON1\r\n+#define MT6358_BUCK_VPA_DBG0 0x1792\r\n+#define MT6358_BUCK_VPA_DBG1 0x1794\r\n+#define MT6358_VPROC_ANA_CON0 0x180c\r\n+#define MT6358_VCORE_VGPU_ANA_CON0 0x1828\r\n+#define MT6358_VMODEM_ANA_CON0 0x1888\r\n+#define MT6358_VDRAM1_ANA_CON0 0x1896\r\n+#define MT6358_VS1_ANA_CON0 0x18a2\r\n+#define MT6358_VS2_ANA_CON0 0x18ae\r\n+#define MT6358_VPA_ANA_CON0 0x18ba\r\n+#define MT6358_LDO_TOP_INT_CON0 0x1a50\r\n+#define MT6358_LDO_TOP_INT_CON1 0x1a56\r\n+#define MT6358_LDO_TOP_INT_STATUS0 0x1a68\r\n+#define MT6358_LDO_TOP_INT_STATUS1 0x1a6a\r\n+#define MT6358_LDO_VXO22_CON0 0x1a88\r\n+#define MT6358_LDO_VXO22_CON1 0x1a96\r\n+#define MT6358_LDO_VA12_CON0 0x1a9c\r\n+#define MT6358_LDO_VA12_CON1 0x1aaa\r\n+#define MT6358_LDO_VAUX18_CON0 0x1ab0\r\n+#define MT6358_LDO_VAUX18_CON1 0x1abe\r\n+#define MT6358_LDO_VAUD28_CON0 0x1ac4\r\n+#define MT6358_LDO_VAUD28_CON1 0x1ad2\r\n+#define MT6358_LDO_VIO28_CON0 0x1ad8\r\n+#define MT6358_LDO_VIO28_CON1 0x1ae6\r\n+#define MT6358_LDO_VIO18_CON0 0x1aec\r\n+#define MT6358_LDO_VIO18_CON1 0x1afa\r\n+#define MT6358_LDO_VDRAM2_CON0 0x1b08\r\n+#define MT6358_LDO_VDRAM2_CON1 0x1b16\r\n+#define MT6358_LDO_VEMC_CON0 0x1b1c\r\n+#define MT6358_LDO_VEMC_CON1 0x1b2a\r\n+#define MT6358_LDO_VUSB_CON0_0 0x1b30\r\n+#define MT6358_LDO_VUSB_CON1 0x1b40\r\n+#define MT6358_LDO_VSRAM_PROC11_CON0 0x1b46\r\n+#define MT6358_LDO_VSRAM_PROC11_DBG0 0x1b60\r\n+#define MT6358_LDO_VSRAM_PROC11_DBG1 0x1b62\r\n+#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON0 0x1b64\r\n+#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON1 0x1b66\r\n+#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON2 0x1b68\r\n+#define MT6358_LDO_VSRAM_PROC11_TRACKING_CON3 0x1b6a\r\n+#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON0 0x1b6c\r\n+#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON1 0x1b6e\r\n+#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON2 0x1b70\r\n+#define MT6358_LDO_VSRAM_PROC12_TRACKING_CON3 0x1b72\r\n+#define MT6358_LDO_VSRAM_WAKEUP_CON0 0x1b74\r\n+#define MT6358_LDO_GON1_ELR_NUM 0x1b76\r\n+#define MT6358_LDO_VDRAM2_ELR0 0x1b78\r\n+#define MT6358_LDO_VSRAM_PROC12_CON0 0x1b88\r\n+#define MT6358_LDO_VSRAM_PROC12_DBG0 0x1ba2\r\n+#define MT6358_LDO_VSRAM_PROC12_DBG1 0x1ba4\r\n+#define MT6358_LDO_VSRAM_OTHERS_CON0 0x1ba6\r\n+#define MT6358_LDO_VSRAM_OTHERS_DBG0 0x1bc0\r\n+#define MT6358_LDO_VSRAM_OTHERS_DBG1 0x1bc2\r\n+#define MT6358_LDO_VSRAM_GPU_CON0 0x1bc8\r\n+#define MT6358_LDO_VSRAM_GPU_DBG0 0x1be2\r\n+#define MT6358_LDO_VSRAM_GPU_DBG1 0x1be4\r\n+#define MT6358_LDO_VSRAM_CON0 0x1bee\r\n+#define MT6358_LDO_VSRAM_CON1 0x1bf0\r\n+#define MT6358_LDO_VSRAM_CON2 0x1bf2\r\n+#define MT6358_LDO_VSRAM_CON3 0x1bf4\r\n+#define MT6358_LDO_VFE28_CON0 0x1c08\r\n+#define MT6358_LDO_VFE28_CON1 0x1c16\r\n+#define MT6358_LDO_VFE28_CON2 0x1c18\r\n+#define MT6358_LDO_VFE28_CON3 0x1c1a\r\n+#define MT6358_LDO_VRF18_CON0 0x1c1c\r\n+#define MT6358_LDO_VRF18_CON1 0x1c2a\r\n+#define MT6358_LDO_VRF18_CON2 0x1c2c\r\n+#define MT6358_LDO_VRF18_CON3 0x1c2e\r\n+#define MT6358_LDO_VRF12_CON0 0x1c30\r\n+#define MT6358_LDO_VRF12_CON1 0x1c3e\r\n+#define MT6358_LDO_VRF12_CON2 0x1c40\r\n+#define MT6358_LDO_VRF12_CON3 0x1c42\r\n+#define MT6358_LDO_VEFUSE_CON0 0x1c44\r\n+#define MT6358_LDO_VEFUSE_CON1 0x1c52\r\n+#define MT6358_LDO_VEFUSE_CON2 0x1c54\r\n+#define MT6358_LDO_VEFUSE_CON3 0x1c56\r\n+#define MT6358_LDO_VCN18_CON0 0x1c58\r\n+#define MT6358_LDO_VCN18_CON1 0x1c66\r\n+#define MT6358_LDO_VCN18_CON2 0x1c68\r\n+#define MT6358_LDO_VCN18_CON3 0x1c6a\r\n+#define MT6358_LDO_VCAMA1_CON0 0x1c6c\r\n+#define MT6358_LDO_VCAMA1_CON1 0x1c7a\r\n+#define MT6358_LDO_VCAMA1_CON2 0x1c7c\r\n+#define MT6358_LDO_VCAMA1_CON3 0x1c7e\r\n+#define MT6358_LDO_VCAMA2_CON0 0x1c88\r\n+#define MT6358_LDO_VCAMA2_CON1 0x1c96\r\n+#define MT6358_LDO_VCAMA2_CON2 0x1c98\r\n+#define MT6358_LDO_VCAMA2_CON3 0x1c9a\r\n+#define MT6358_LDO_VCAMD_CON0 0x1c9c\r\n+#define MT6358_LDO_VCAMD_CON1 0x1caa\r\n+#define MT6358_LDO_VCAMD_CON2 0x1cac\r\n+#define MT6358_LDO_VCAMD_CON3 0x1cae\r\n+#define MT6358_LDO_VCAMIO_CON0 0x1cb0\r\n+#define MT6358_LDO_VCAMIO_CON1 0x1cbe\r\n+#define MT6358_LDO_VCAMIO_CON2 0x1cc0\r\n+#define MT6358_LDO_VCAMIO_CON3 0x1cc2\r\n+#define MT6358_LDO_VMC_CON0 0x1cc4\r\n+#define MT6358_LDO_VMC_CON1 0x1cd2\r\n+#define MT6358_LDO_VMC_CON2 0x1cd4\r\n+#define MT6358_LDO_VMC_CON3 0x1cd6\r\n+#define MT6358_LDO_VMCH_CON0 0x1cd8\r\n+#define MT6358_LDO_VMCH_CON1 0x1ce6\r\n+#define MT6358_LDO_VMCH_CON2 0x1ce8\r\n+#define MT6358_LDO_VMCH_CON3 0x1cea\r\n+#define MT6358_LDO_VIBR_CON0 0x1d08\r\n+#define MT6358_LDO_VIBR_CON1 0x1d16\r\n+#define MT6358_LDO_VIBR_CON2 0x1d18\r\n+#define MT6358_LDO_VIBR_CON3 0x1d1a\r\n+#define MT6358_LDO_VCN33_CON0_0 0x1d1c\r\n+#define MT6358_LDO_VCN33_CON0_1 0x1d2a\r\n+#define MT6358_LDO_VCN33_CON1 0x1d2c\r\n+#define MT6358_LDO_VCN33_BT_CON1 MT6358_LDO_VCN33_CON1\r\n+#define MT6358_LDO_VCN33_WIFI_CON1 MT6358_LDO_VCN33_CON1\r\n+#define MT6358_LDO_VCN33_CON2 0x1d2e\r\n+#define MT6358_LDO_VCN33_CON3 0x1d30\r\n+#define MT6358_LDO_VLDO28_CON0_0 0x1d32\r\n+#define MT6358_LDO_VLDO28_CON0_1 0x1d40\r\n+#define MT6358_LDO_VLDO28_CON1 0x1d42\r\n+#define MT6358_LDO_VLDO28_CON2 0x1d44\r\n+#define MT6358_LDO_VLDO28_CON3 0x1d46\r\n+#define MT6358_LDO_VSIM1_CON0 0x1d48\r\n+#define MT6358_LDO_VSIM1_CON1 0x1d56\r\n+#define MT6358_LDO_VSIM1_CON2 0x1d58\r\n+#define MT6358_LDO_VSIM1_CON3 0x1d5a\r\n+#define MT6358_LDO_VSIM2_CON0 0x1d5c\r\n+#define MT6358_LDO_VSIM2_CON1 0x1d6a\r\n+#define MT6358_LDO_VSIM2_CON2 0x1d6c\r\n+#define MT6358_LDO_VSIM2_CON3 0x1d6e\r\n+#define MT6358_LDO_VCN28_CON0 0x1d88\r\n+#define MT6358_LDO_VCN28_CON1 0x1d96\r\n+#define MT6358_LDO_VCN28_CON2 0x1d98\r\n+#define MT6358_LDO_VCN28_CON3 0x1d9a\r\n+#define MT6358_VRTC28_CON0 0x1d9c\r\n+#define MT6358_LDO_VBIF28_CON0 0x1d9e\r\n+#define MT6358_LDO_VBIF28_CON1 0x1dac\r\n+#define MT6358_LDO_VBIF28_CON2 0x1dae\r\n+#define MT6358_LDO_VBIF28_CON3 0x1db0\r\n+#define MT6358_VCAMA1_ANA_CON0 0x1e08\r\n+#define MT6358_VCAMA2_ANA_CON0 0x1e0c\r\n+#define MT6358_VCN33_ANA_CON0 0x1e28\r\n+#define MT6358_VSIM1_ANA_CON0 0x1e2c\r\n+#define MT6358_VSIM2_ANA_CON0 0x1e30\r\n+#define MT6358_VUSB_ANA_CON0 0x1e34\r\n+#define MT6358_VEMC_ANA_CON0 0x1e38\r\n+#define MT6358_VLDO28_ANA_CON0 0x1e3c\r\n+#define MT6358_VIO28_ANA_CON0 0x1e40\r\n+#define MT6358_VIBR_ANA_CON0 0x1e44\r\n+#define MT6358_VMCH_ANA_CON0 0x1e48\r\n+#define MT6358_VMC_ANA_CON0 0x1e4c\r\n+#define MT6358_VRF18_ANA_CON0 0x1e88\r\n+#define MT6358_VCN18_ANA_CON0 0x1e8c\r\n+#define MT6358_VCAMIO_ANA_CON0 0x1e90\r\n+#define MT6358_VIO18_ANA_CON0 0x1e94\r\n+#define MT6358_VEFUSE_ANA_CON0 0x1e98\r\n+#define MT6358_VRF12_ANA_CON0 0x1e9c\r\n+#define MT6358_VSRAM_PROC11_ANA_CON0 0x1ea0\r\n+#define MT6358_VSRAM_PROC12_ANA_CON0 0x1ea4\r\n+#define MT6358_VSRAM_OTHERS_ANA_CON0 0x1ea6\r\n+#define MT6358_VSRAM_GPU_ANA_CON0 0x1ea8\r\n+#define MT6358_VDRAM2_ANA_CON0 0x1eaa\r\n+#define MT6358_VCAMD_ANA_CON0 0x1eae\r\n+#define MT6358_VA12_ANA_CON0 0x1eb2\r\n+#define MT6358_AUD_TOP_INT_CON0 0x2228\r\n+#define MT6358_AUD_TOP_INT_STATUS0 0x2234\r\n+\r\n+#endif /* __MFD_MT6358_REGISTERS_H__ */\r\ndiff --git a/include/linux/mfd/mt6397/core.h b/include/linux/mfd/mt6397/core.h\r\nindex b81d333..9492685 100644\r\n--- a/include/linux/mfd/mt6397/core.h\r\n+++ b/include/linux/mfd/mt6397/core.h\r\n@@ -12,6 +12,7 @@\r\n \r\n enum chip_id {\r\n \tMT6323_CHIP_ID = 0x23,\r\n+\tMT6358_CHIP_ID = 0x58,\r\n \tMT6391_CHIP_ID = 0x91,\r\n \tMT6397_CHIP_ID = 0x97,\r\n };\r\n@@ -65,8 +66,10 @@ struct mt6397_chip {\r\n \tu16 int_con[2];\r\n \tu16 int_status[2];\r\n \tu16 chip_id;\r\n+\tvoid *irq_data;\r\n };\r\n \r\n+int mt6358_irq_init(struct mt6397_chip *chip);\r\n int mt6397_irq_init(struct mt6397_chip *chip);\r\n \r\n #endif /* __MFD_MT6397_CORE_H__ */\r\n", "prefixes": [ "v12", "4/6" ] }