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GET /api/patches/1213091/?format=api
{ "id": 1213091, "url": "http://patchwork.ozlabs.org/api/patches/1213091/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/77ae9eff4123727c6acf470ac4925da5955cedb8.1576745635.git.matti.vaittinen@fi.rohmeurope.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<77ae9eff4123727c6acf470ac4925da5955cedb8.1576745635.git.matti.vaittinen@fi.rohmeurope.com>", "list_archive_url": null, "date": "2019-12-19T09:50:59", "name": "[v7,05/12] mfd: bd71828: Support ROHM BD71828 PMIC - core", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e59caecc72f1b98a1039855660954502892ef062", "submitter": { "id": 74146, "url": "http://patchwork.ozlabs.org/api/people/74146/?format=api", "name": "Matti Vaittinen", "email": "matti.vaittinen@fi.rohmeurope.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/77ae9eff4123727c6acf470ac4925da5955cedb8.1576745635.git.matti.vaittinen@fi.rohmeurope.com/mbox/", "series": [ { "id": 149534, "url": "http://patchwork.ozlabs.org/api/series/149534/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=149534", "date": "2019-12-19T09:44:08", "name": "Support ROHM BD71828 PMIC", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/149534/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1213091/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1213091/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org; spf=none (no SPF record)\n\tsmtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67;\n\thelo=vger.kernel.org;\n\tenvelope-from=linux-gpio-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=fi.rohmeurope.com" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 47dnFd4t8pz9sPn\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 19 Dec 2019 20:51:17 +1100 (AEDT)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1726652AbfLSJvN (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tThu, 19 Dec 2019 04:51:13 -0500", "from mail-lj1-f195.google.com ([209.85.208.195]:33475 \"EHLO\n\tmail-lj1-f195.google.com\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S1726722AbfLSJvM (ORCPT\n\t<rfc822; linux-gpio@vger.kernel.org>); Thu, 19 Dec 2019 04:51:12 -0500", "by mail-lj1-f195.google.com with SMTP id p8so5540326ljg.0;\n\tThu, 19 Dec 2019 01:51:08 -0800 (PST)", "from localhost.localdomain\n\t(dyt4gctb359myxd0pkwmt-4.rev.dnainternet.fi.\n\t[2001:14bb:430:5140:37cf:5409:8fcc:4495])\n\tby smtp.gmail.com with ESMTPSA id\n\tf11sm2992380lfa.9.2019.12.19.01.51.05\n\t(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n\tThu, 19 Dec 2019 01:51:06 -0800 (PST)" ], "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:date:from:to:cc:subject:message-id:references\n\t:mime-version:content-disposition:in-reply-to:user-agent;\n\tbh=CgY/DNrg1Rn+GiI7obtlHRXJoY+CMABK1PqaSbNZ/bI=;\n\tb=SnVVtZSKbj+pZ0K5+Eb28O2FE82OlMz5HDpSWMoKaZTQMW/YLIn8FX7iEL5MSOJpcj\n\tu/yOgD58LUTGxLTC5WFt6dANve3H/qtcl6zSpb/wN11qWmPrUjBcDr+qmlwPbJhypZ4R\n\tCMjvN3vygSCoXdOQTY+IuCvh0WzL0gQS0VVXoPFGgFAdARvjgDNrlHhYcVkuNu2al9Lc\n\tiIt/hCGgnGxtIbLAoOXTbUNtVLg40UVOWtXq9ke69g7D7TNu/4WUvtWEtURUirOzffGd\n\t7qASE8/dxOvrZKJZ4QCO9UMXytk3/ZVFPNLfw+pb95RmNd7NDtsJbX7yREbIa22pUh/D\n\tQUOw==", "X-Gm-Message-State": "APjAAAWmAHSCVgpahIOiW3OXpm09DYtYQJtdKhqyQYCdfKIV9rIUnmnG\n\tWdhjg52CiWWaNkAH8M+5VKE=", "X-Google-Smtp-Source": "APXvYqyH5gZT30Jxs3nWVKjLNNYwVUBNPcKWmy93fd90MMF4DAJbpWf/RclOfN9M8jCMx/iR+UgC5w==", "X-Received": "by 2002:a2e:9041:: with SMTP id n1mr5289099ljg.133.1576749067268;\n\tThu, 19 Dec 2019 01:51:07 -0800 (PST)", "Date": "Thu, 19 Dec 2019 11:50:59 +0200", "From": "Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>", "To": "matti.vaittinen@fi.rohmeurope.com, mazziesaccount@gmail.com", "Cc": "Jacek Anaszewski <jacek.anaszewski@gmail.com>,\n\tPavel Machek <pavel@ucw.cz>, Dan Murphy <dmurphy@ti.com>,\n\tRob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>,\n\tLee Jones <lee.jones@linaro.org>,\n\tMichael Turquette <mturquette@baylibre.com>,\n\tStephen Boyd <sboyd@kernel.org>,\n\tLinus Walleij <linus.walleij@linaro.org>,\n\tBartosz Golaszewski <bgolaszewski@baylibre.com>,\n\tLiam Girdwood <lgirdwood@gmail.com>, Mark Brown <broonie@kernel.org>,\n\tAlessandro Zummo <a.zummo@towertech.it>,\n\tAlexandre Belloni <alexandre.belloni@bootlin.com>,\n\tlinux-leds@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,\n\tlinux-gpio@vger.kernel.org, linux-rtc@vger.kernel.org", "Subject": "[PATCH v7 05/12] mfd: bd71828: Support ROHM BD71828 PMIC - core", "Message-ID": "<77ae9eff4123727c6acf470ac4925da5955cedb8.1576745635.git.matti.vaittinen@fi.rohmeurope.com>", "References": "<cover.1576745635.git.matti.vaittinen@fi.rohmeurope.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=us-ascii", "Content-Disposition": "inline", "In-Reply-To": "<cover.1576745635.git.matti.vaittinen@fi.rohmeurope.com>", "User-Agent": "Mutt/1.12.1 (2019-06-15)", "Sender": "linux-gpio-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "BD71828GW is a single-chip power management IC for battery-powered portable\ndevices. The IC integrates 7 buck converters, 7 LDOs, and a 1500 mA\nsingle-cell linear charger. Also included is a Coulomb counter, a real-time\nclock (RTC), 3 GPO/regulator control pins, HALL input and a 32.768 kHz\nclock gate.\n\nAdd MFD core driver providing interrupt controller facilities and i2c\naccess to sub device drivers.\n\nSigned-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>\nAcked-for-MFD-by: Lee Jones <lee.jones@linaro.org>\n---\n\nChanges since v6:\n- remove unnecessary newline from driver and Makefile\n\n drivers/mfd/Kconfig | 15 ++\n drivers/mfd/Makefile | 1 +\n drivers/mfd/rohm-bd71828.c | 318 +++++++++++++++++++++++\n include/linux/mfd/rohm-bd71828.h | 425 +++++++++++++++++++++++++++++++\n include/linux/mfd/rohm-generic.h | 1 +\n 5 files changed, 760 insertions(+)\n create mode 100644 drivers/mfd/rohm-bd71828.c\n create mode 100644 include/linux/mfd/rohm-bd71828.h", "diff": "diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig\nindex 420900852166..c3c9432ef51c 100644\n--- a/drivers/mfd/Kconfig\n+++ b/drivers/mfd/Kconfig\n@@ -1906,6 +1906,21 @@ config MFD_ROHM_BD70528\n \t 10 bits SAR ADC for battery temperature monitor and 1S battery\n \t charger.\n \n+config MFD_ROHM_BD71828\n+\ttristate \"ROHM BD71828 Power Management IC\"\n+\tdepends on I2C=y\n+\tdepends on OF\n+\tselect REGMAP_I2C\n+\tselect REGMAP_IRQ\n+\tselect MFD_CORE\n+\thelp\n+\t Select this option to get support for the ROHM BD71828 Power\n+\t Management IC. BD71828GW is a single-chip power management IC for\n+\t battery-powered portable devices. The IC integrates 7 buck\n+\t converters, 7 LDOs, and a 1500 mA single-cell linear charger.\n+\t Also included is a Coulomb counter, a real-time clock (RTC), and\n+\t a 32.768 kHz clock gate.\n+\n config MFD_STM32_LPTIMER\n \ttristate \"Support for STM32 Low-Power Timer\"\n \tdepends on (ARCH_STM32 && OF) || COMPILE_TEST\ndiff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile\nindex aed99f08739f..61b3093af39d 100644\n--- a/drivers/mfd/Makefile\n+++ b/drivers/mfd/Makefile\n@@ -252,6 +252,7 @@ obj-$(CONFIG_MFD_MXS_LRADC) += mxs-lradc.o\n obj-$(CONFIG_MFD_SC27XX_PMIC)\t+= sprd-sc27xx-spi.o\n obj-$(CONFIG_RAVE_SP_CORE)\t+= rave-sp.o\n obj-$(CONFIG_MFD_ROHM_BD70528)\t+= rohm-bd70528.o\n+obj-$(CONFIG_MFD_ROHM_BD71828)\t+= rohm-bd71828.o\n obj-$(CONFIG_MFD_ROHM_BD718XX)\t+= rohm-bd718x7.o\n obj-$(CONFIG_MFD_STMFX) \t+= stmfx.o\n \ndiff --git a/drivers/mfd/rohm-bd71828.c b/drivers/mfd/rohm-bd71828.c\nnew file mode 100644\nindex 000000000000..0ec386c9f26b\n--- /dev/null\n+++ b/drivers/mfd/rohm-bd71828.c\n@@ -0,0 +1,318 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+//\n+// Copyright (C) 2019 ROHM Semiconductors\n+//\n+// ROHM BD71828 PMIC driver\n+\n+#include <linux/i2c.h>\n+#include <linux/interrupt.h>\n+#include <linux/ioport.h>\n+#include <linux/irq.h>\n+#include <linux/mfd/core.h>\n+#include <linux/mfd/rohm-bd71828.h>\n+#include <linux/module.h>\n+#include <linux/of_device.h>\n+#include <linux/regmap.h>\n+#include <linux/types.h>\n+\n+static const struct resource rtc_irqs[] = {\n+\tDEFINE_RES_IRQ_NAMED(BD71828_INT_RTC0, \"bd71828-rtc-alm-0\"),\n+\tDEFINE_RES_IRQ_NAMED(BD71828_INT_RTC1, \"bd71828-rtc-alm-1\"),\n+\tDEFINE_RES_IRQ_NAMED(BD71828_INT_RTC2, \"bd71828-rtc-alm-2\"),\n+};\n+\n+static struct mfd_cell bd71828_mfd_cells[] = {\n+\t{ .name = \"bd71828-pmic\", },\n+\t{ .name = \"bd71828-gpio\", },\n+\t{ .name = \"bd71828-led\", .of_compatible = \"rohm,bd71828-leds\" },\n+\t/*\n+\t * We use BD71837 driver to drive the clock block. Only differences to\n+\t * BD70528 clock gate are the register address and mask.\n+\t */\n+\t{ .name = \"bd71828-clk\", },\n+\t{ .name = \"bd71827-power\", },\n+\t{\n+\t\t.name = \"bd71828-rtc\",\n+\t\t.resources = rtc_irqs,\n+\t\t.num_resources = ARRAY_SIZE(rtc_irqs),\n+\t},\n+};\n+\n+static const struct regmap_range volatile_ranges[] = {\n+\t{\n+\t\t.range_min = BD71828_REG_PS_CTRL_1,\n+\t\t.range_max = BD71828_REG_PS_CTRL_1,\n+\t}, {\n+\t\t.range_min = BD71828_REG_PS_CTRL_3,\n+\t\t.range_max = BD71828_REG_PS_CTRL_3,\n+\t}, {\n+\t\t.range_min = BD71828_REG_RTC_SEC,\n+\t\t.range_max = BD71828_REG_RTC_YEAR,\n+\t}, {\n+\t\t/*\n+\t\t * For now make all charger registers volatile because many\n+\t\t * needs to be and because the charger block is not that\n+\t\t * performance critical.\n+\t\t */\n+\t\t.range_min = BD71828_REG_CHG_STATE,\n+\t\t.range_max = BD71828_REG_CHG_FULL,\n+\t}, {\n+\t\t.range_min = BD71828_REG_INT_MAIN,\n+\t\t.range_max = BD71828_REG_IO_STAT,\n+\t},\n+};\n+\n+static const struct regmap_access_table volatile_regs = {\n+\t.yes_ranges = &volatile_ranges[0],\n+\t.n_yes_ranges = ARRAY_SIZE(volatile_ranges),\n+};\n+\n+static struct regmap_config bd71828_regmap = {\n+\t.reg_bits = 8,\n+\t.val_bits = 8,\n+\t.volatile_table = &volatile_regs,\n+\t.max_register = BD71828_MAX_REGISTER,\n+\t.cache_type = REGCACHE_RBTREE,\n+};\n+\n+/*\n+ * Mapping of main IRQ register bits to sub-IRQ register offsets so that we can\n+ * access corect sub-IRQ registers based on bits that are set in main IRQ\n+ * register.\n+ */\n+\n+static unsigned int bit0_offsets[] = {11};\t\t/* RTC IRQ */\n+static unsigned int bit1_offsets[] = {10};\t\t/* TEMP IRQ */\n+static unsigned int bit2_offsets[] = {6, 7, 8, 9};\t/* BAT MON IRQ */\n+static unsigned int bit3_offsets[] = {5};\t\t/* BAT IRQ */\n+static unsigned int bit4_offsets[] = {4};\t\t/* CHG IRQ */\n+static unsigned int bit5_offsets[] = {3};\t\t/* VSYS IRQ */\n+static unsigned int bit6_offsets[] = {1, 2};\t\t/* DCIN IRQ */\n+static unsigned int bit7_offsets[] = {0};\t\t/* BUCK IRQ */\n+\n+static struct regmap_irq_sub_irq_map bd71828_sub_irq_offsets[] = {\n+\tREGMAP_IRQ_MAIN_REG_OFFSET(bit0_offsets),\n+\tREGMAP_IRQ_MAIN_REG_OFFSET(bit1_offsets),\n+\tREGMAP_IRQ_MAIN_REG_OFFSET(bit2_offsets),\n+\tREGMAP_IRQ_MAIN_REG_OFFSET(bit3_offsets),\n+\tREGMAP_IRQ_MAIN_REG_OFFSET(bit4_offsets),\n+\tREGMAP_IRQ_MAIN_REG_OFFSET(bit5_offsets),\n+\tREGMAP_IRQ_MAIN_REG_OFFSET(bit6_offsets),\n+\tREGMAP_IRQ_MAIN_REG_OFFSET(bit7_offsets),\n+};\n+\n+static struct regmap_irq bd71828_irqs[] = {\n+\tREGMAP_IRQ_REG(BD71828_INT_BUCK1_OCP, 0, BD71828_INT_BUCK1_OCP_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BUCK2_OCP, 0, BD71828_INT_BUCK2_OCP_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BUCK3_OCP, 0, BD71828_INT_BUCK3_OCP_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BUCK4_OCP, 0, BD71828_INT_BUCK4_OCP_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BUCK5_OCP, 0, BD71828_INT_BUCK5_OCP_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BUCK6_OCP, 0, BD71828_INT_BUCK6_OCP_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BUCK7_OCP, 0, BD71828_INT_BUCK7_OCP_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_PGFAULT, 0, BD71828_INT_PGFAULT_MASK),\n+\t/* DCIN1 interrupts */\n+\tREGMAP_IRQ_REG(BD71828_INT_DCIN_DET, 1, BD71828_INT_DCIN_DET_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_DCIN_RMV, 1, BD71828_INT_DCIN_RMV_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_CLPS_OUT, 1, BD71828_INT_CLPS_OUT_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_CLPS_IN, 1, BD71828_INT_CLPS_IN_MASK),\n+\t/* DCIN2 interrupts */\n+\tREGMAP_IRQ_REG(BD71828_INT_DCIN_MON_RES, 2,\n+\t\t BD71828_INT_DCIN_MON_RES_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_DCIN_MON_DET, 2,\n+\t\t BD71828_INT_DCIN_MON_DET_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_LONGPUSH, 2, BD71828_INT_LONGPUSH_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_MIDPUSH, 2, BD71828_INT_MIDPUSH_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_SHORTPUSH, 2, BD71828_INT_SHORTPUSH_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_PUSH, 2, BD71828_INT_PUSH_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_WDOG, 2, BD71828_INT_WDOG_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_SWRESET, 2, BD71828_INT_SWRESET_MASK),\n+\t/* Vsys */\n+\tREGMAP_IRQ_REG(BD71828_INT_VSYS_UV_RES, 3,\n+\t\t BD71828_INT_VSYS_UV_RES_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_VSYS_UV_DET, 3,\n+\t\t BD71828_INT_VSYS_UV_DET_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_RES, 3,\n+\t\t BD71828_INT_VSYS_LOW_RES_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_VSYS_LOW_DET, 3,\n+\t\t BD71828_INT_VSYS_LOW_DET_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_IN, 3,\n+\t\t BD71828_INT_VSYS_HALL_IN_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_VSYS_HALL_TOGGLE, 3,\n+\t\t BD71828_INT_VSYS_HALL_TOGGLE_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_VSYS_MON_RES, 3,\n+\t\t BD71828_INT_VSYS_MON_RES_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_VSYS_MON_DET, 3,\n+\t\t BD71828_INT_VSYS_MON_DET_MASK),\n+\t/* Charger */\n+\tREGMAP_IRQ_REG(BD71828_INT_CHG_DCIN_ILIM, 4,\n+\t\t BD71828_INT_CHG_DCIN_ILIM_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_CHG_TOPOFF_TO_DONE, 4,\n+\t\t BD71828_INT_CHG_TOPOFF_TO_DONE_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TEMP, 4,\n+\t\t BD71828_INT_CHG_WDG_TEMP_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_CHG_WDG_TIME, 4,\n+\t\t BD71828_INT_CHG_WDG_TIME_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_RES, 4,\n+\t\t BD71828_INT_CHG_RECHARGE_RES_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_CHG_RECHARGE_DET, 4,\n+\t\t BD71828_INT_CHG_RECHARGE_DET_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_CHG_RANGED_TEMP_TRANSITION, 4,\n+\t\t BD71828_INT_CHG_RANGED_TEMP_TRANSITION_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_CHG_STATE_TRANSITION, 4,\n+\t\t BD71828_INT_CHG_STATE_TRANSITION_MASK),\n+\t/* Battery */\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_NORMAL, 5,\n+\t\t BD71828_INT_BAT_TEMP_NORMAL_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_ERANGE, 5,\n+\t\t BD71828_INT_BAT_TEMP_ERANGE_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_TEMP_WARN, 5,\n+\t\t BD71828_INT_BAT_TEMP_WARN_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_REMOVED, 5,\n+\t\t BD71828_INT_BAT_REMOVED_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_DETECTED, 5,\n+\t\t BD71828_INT_BAT_DETECTED_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_THERM_REMOVED, 5,\n+\t\t BD71828_INT_THERM_REMOVED_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_THERM_DETECTED, 5,\n+\t\t BD71828_INT_THERM_DETECTED_MASK),\n+\t/* Battery Mon 1 */\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_DEAD, 6, BD71828_INT_BAT_DEAD_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_RES, 6,\n+\t\t BD71828_INT_BAT_SHORTC_RES_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_SHORTC_DET, 6,\n+\t\t BD71828_INT_BAT_SHORTC_DET_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_RES, 6,\n+\t\t BD71828_INT_BAT_LOW_VOLT_RES_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_LOW_VOLT_DET, 6,\n+\t\t BD71828_INT_BAT_LOW_VOLT_DET_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_RES, 6,\n+\t\t BD71828_INT_BAT_OVER_VOLT_RES_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_OVER_VOLT_DET, 6,\n+\t\t BD71828_INT_BAT_OVER_VOLT_DET_MASK),\n+\t/* Battery Mon 2 */\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_MON_RES, 7,\n+\t\t BD71828_INT_BAT_MON_RES_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_MON_DET, 7,\n+\t\t BD71828_INT_BAT_MON_DET_MASK),\n+\t/* Battery Mon 3 (Coulomb counter) */\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON1, 8,\n+\t\t BD71828_INT_BAT_CC_MON1_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON2, 8,\n+\t\t BD71828_INT_BAT_CC_MON2_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_CC_MON3, 8,\n+\t\t BD71828_INT_BAT_CC_MON3_MASK),\n+\t/* Battery Mon 4 */\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_RES, 9,\n+\t\t BD71828_INT_BAT_OVER_CURR_1_RES_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_1_DET, 9,\n+\t\t BD71828_INT_BAT_OVER_CURR_1_DET_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_RES, 9,\n+\t\t BD71828_INT_BAT_OVER_CURR_2_RES_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_2_DET, 9,\n+\t\t BD71828_INT_BAT_OVER_CURR_2_DET_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_RES, 9,\n+\t\t BD71828_INT_BAT_OVER_CURR_3_RES_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_BAT_OVER_CURR_3_DET, 9,\n+\t\t BD71828_INT_BAT_OVER_CURR_3_DET_MASK),\n+\t/* Temperature */\n+\tREGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_RES, 10,\n+\t\t BD71828_INT_TEMP_BAT_LOW_RES_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_LOW_DET, 10,\n+\t\t BD71828_INT_TEMP_BAT_LOW_DET_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_RES, 10,\n+\t\t BD71828_INT_TEMP_BAT_HI_RES_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_TEMP_BAT_HI_DET, 10,\n+\t\t BD71828_INT_TEMP_BAT_HI_DET_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_RES, 10,\n+\t\t BD71828_INT_TEMP_CHIP_OVER_125_RES_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_125_DET, 10,\n+\t\t BD71828_INT_TEMP_CHIP_OVER_125_DET_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_DET, 10,\n+\t\t BD71828_INT_TEMP_CHIP_OVER_VF_DET_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_TEMP_CHIP_OVER_VF_RES, 10,\n+\t\t BD71828_INT_TEMP_CHIP_OVER_VF_RES_MASK),\n+\t/* RTC Alarm */\n+\tREGMAP_IRQ_REG(BD71828_INT_RTC0, 11, BD71828_INT_RTC0_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_RTC1, 11, BD71828_INT_RTC1_MASK),\n+\tREGMAP_IRQ_REG(BD71828_INT_RTC2, 11, BD71828_INT_RTC2_MASK),\n+};\n+\n+static struct regmap_irq_chip bd71828_irq_chip = {\n+\t.name = \"bd71828_irq\",\n+\t.main_status = BD71828_REG_INT_MAIN,\n+\t.irqs = &bd71828_irqs[0],\n+\t.num_irqs = ARRAY_SIZE(bd71828_irqs),\n+\t.status_base = BD71828_REG_INT_BUCK,\n+\t.mask_base = BD71828_REG_INT_MASK_BUCK,\n+\t.ack_base = BD71828_REG_INT_BUCK,\n+\t.mask_invert = true,\n+\t.init_ack_masked = true,\n+\t.num_regs = 12,\n+\t.num_main_regs = 1,\n+\t.sub_reg_offsets = &bd71828_sub_irq_offsets[0],\n+\t.num_main_status_bits = 8,\n+\t.irq_reg_stride = 1,\n+};\n+\n+static int bd71828_i2c_probe(struct i2c_client *i2c)\n+{\n+\tstruct rohm_regmap_dev *chip;\n+\tstruct regmap_irq_chip_data *irq_data;\n+\tint ret;\n+\n+\tif (!i2c->irq) {\n+\t\tdev_err(&i2c->dev, \"No IRQ configured\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tchip = devm_kzalloc(&i2c->dev, sizeof(*chip), GFP_KERNEL);\n+\tif (!chip)\n+\t\treturn -ENOMEM;\n+\n+\tdev_set_drvdata(&i2c->dev, chip);\n+\n+\tchip->regmap = devm_regmap_init_i2c(i2c, &bd71828_regmap);\n+\tif (IS_ERR(chip->regmap)) {\n+\t\tdev_err(&i2c->dev, \"Failed to initialize Regmap\\n\");\n+\t\treturn PTR_ERR(chip->regmap);\n+\t}\n+\n+\tret = devm_regmap_add_irq_chip(&i2c->dev, chip->regmap,\n+\t\t\t\t i2c->irq, IRQF_ONESHOT, 0,\n+\t\t\t\t &bd71828_irq_chip, &irq_data);\n+\tif (ret) {\n+\t\tdev_err(&i2c->dev, \"Failed to add IRQ chip\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\tdev_dbg(&i2c->dev, \"Registered %d IRQs for chip\\n\",\n+\t\tbd71828_irq_chip.num_irqs);\n+\n+\tret = devm_mfd_add_devices(&i2c->dev, PLATFORM_DEVID_AUTO,\n+\t\t\t\t bd71828_mfd_cells,\n+\t\t\t\t ARRAY_SIZE(bd71828_mfd_cells), NULL, 0,\n+\t\t\t\t regmap_irq_get_domain(irq_data));\n+\tif (ret)\n+\t\tdev_err(&i2c->dev, \"Failed to create subdevices\\n\");\n+\n+\treturn ret;\n+}\n+\n+static const struct of_device_id bd71828_of_match[] = {\n+\t{ .compatible = \"rohm,bd71828\", },\n+\t{ },\n+};\n+MODULE_DEVICE_TABLE(of, bd71828_of_match);\n+\n+static struct i2c_driver bd71828_drv = {\n+\t.driver = {\n+\t\t.name = \"rohm-bd71828\",\n+\t\t.of_match_table = bd71828_of_match,\n+\t},\n+\t.probe_new = &bd71828_i2c_probe,\n+};\n+module_i2c_driver(bd71828_drv);\n+\n+MODULE_AUTHOR(\"Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>\");\n+MODULE_DESCRIPTION(\"ROHM BD71828 Power Management IC driver\");\n+MODULE_LICENSE(\"GPL\");\ndiff --git a/include/linux/mfd/rohm-bd71828.h b/include/linux/mfd/rohm-bd71828.h\nnew file mode 100644\nindex 000000000000..eb0557eb5314\n--- /dev/null\n+++ b/include/linux/mfd/rohm-bd71828.h\n@@ -0,0 +1,425 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+/* Copyright (C) 2019 ROHM Semiconductors */\n+\n+#ifndef __LINUX_MFD_BD71828_H__\n+#define __LINUX_MFD_BD71828_H__\n+\n+#include <linux/mfd/rohm-generic.h>\n+\n+/* Regulator IDs */\n+enum {\n+\tBD71828_BUCK1,\n+\tBD71828_BUCK2,\n+\tBD71828_BUCK3,\n+\tBD71828_BUCK4,\n+\tBD71828_BUCK5,\n+\tBD71828_BUCK6,\n+\tBD71828_BUCK7,\n+\tBD71828_LDO1,\n+\tBD71828_LDO2,\n+\tBD71828_LDO3,\n+\tBD71828_LDO4,\n+\tBD71828_LDO5,\n+\tBD71828_LDO6,\n+\tBD71828_LDO_SNVS,\n+\tBD71828_REGULATOR_AMOUNT,\n+};\n+\n+#define BD71828_BUCK1267_VOLTS\t\t0xEF\n+#define BD71828_BUCK3_VOLTS\t\t0x10\n+#define BD71828_BUCK4_VOLTS\t\t0x20\n+#define BD71828_BUCK5_VOLTS\t\t0x10\n+#define BD71828_LDO_VOLTS\t\t0x32\n+/* LDO6 is fixed 1.8V voltage */\n+#define BD71828_LDO_6_VOLTAGE\t\t1800000\n+\n+/* Registers and masks*/\n+\n+/* MODE control */\n+#define BD71828_REG_PS_CTRL_1\t\t0x04\n+#define BD71828_REG_PS_CTRL_2\t\t0x05\n+#define BD71828_REG_PS_CTRL_3\t\t0x06\n+\n+//#define BD71828_REG_SWRESET\t\t0x06\n+#define BD71828_MASK_RUN_LVL_CTRL\t0x30\n+\n+/* Regulator control masks */\n+\n+#define BD71828_MASK_RAMP_DELAY\t\t0x6\n+\n+#define BD71828_MASK_RUN_EN\t\t0x08\n+#define BD71828_MASK_SUSP_EN\t\t0x04\n+#define BD71828_MASK_IDLE_EN\t\t0x02\n+#define BD71828_MASK_LPSR_EN\t\t0x01\n+\n+#define BD71828_MASK_RUN0_EN\t\t0x01\n+#define BD71828_MASK_RUN1_EN\t\t0x02\n+#define BD71828_MASK_RUN2_EN\t\t0x04\n+#define BD71828_MASK_RUN3_EN\t\t0x08\n+\n+#define BD71828_MASK_DVS_BUCK1_CTRL\t0x10\n+#define BD71828_DVS_BUCK1_CTRL_I2C\t0\n+#define BD71828_DVS_BUCK1_USE_RUNLVL\t0x10\n+\n+#define BD71828_MASK_DVS_BUCK2_CTRL\t0x20\n+#define BD71828_DVS_BUCK2_CTRL_I2C\t0\n+#define BD71828_DVS_BUCK2_USE_RUNLVL\t0x20\n+\n+#define BD71828_MASK_DVS_BUCK6_CTRL\t0x40\n+#define BD71828_DVS_BUCK6_CTRL_I2C\t0\n+#define BD71828_DVS_BUCK6_USE_RUNLVL\t0x40\n+\n+#define BD71828_MASK_DVS_BUCK7_CTRL\t0x80\n+#define BD71828_DVS_BUCK7_CTRL_I2C\t0\n+#define BD71828_DVS_BUCK7_USE_RUNLVL\t0x80\n+\n+#define BD71828_MASK_BUCK1267_VOLT\t0xff\n+#define BD71828_MASK_BUCK3_VOLT\t\t0x1f\n+#define BD71828_MASK_BUCK4_VOLT\t\t0x3f\n+#define BD71828_MASK_BUCK5_VOLT\t\t0x1f\n+#define BD71828_MASK_LDO_VOLT\t\t0x3f\n+\n+/* Regulator control regs */\n+#define BD71828_REG_BUCK1_EN\t\t0x08\n+#define BD71828_REG_BUCK1_CTRL\t\t0x09\n+#define BD71828_REG_BUCK1_MODE\t\t0x0a\n+#define BD71828_REG_BUCK1_IDLE_VOLT\t0x0b\n+#define BD71828_REG_BUCK1_SUSP_VOLT\t0x0c\n+#define BD71828_REG_BUCK1_VOLT\t\t0x0d\n+\n+#define BD71828_REG_BUCK2_EN\t\t0x12\n+#define BD71828_REG_BUCK2_CTRL\t\t0x13\n+#define BD71828_REG_BUCK2_MODE\t\t0x14\n+#define BD71828_REG_BUCK2_IDLE_VOLT\t0x15\n+#define BD71828_REG_BUCK2_SUSP_VOLT\t0x16\n+#define BD71828_REG_BUCK2_VOLT\t\t0x17\n+\n+#define BD71828_REG_BUCK3_EN\t\t0x1c\n+#define BD71828_REG_BUCK3_MODE\t\t0x1d\n+#define BD71828_REG_BUCK3_VOLT\t\t0x1e\n+\n+#define BD71828_REG_BUCK4_EN\t\t0x1f\n+#define BD71828_REG_BUCK4_MODE\t\t0x20\n+#define BD71828_REG_BUCK4_VOLT\t\t0x21\n+\n+#define BD71828_REG_BUCK5_EN\t\t0x22\n+#define BD71828_REG_BUCK5_MODE\t\t0x23\n+#define BD71828_REG_BUCK5_VOLT\t\t0x24\n+\n+#define BD71828_REG_BUCK6_EN\t\t0x25\n+#define BD71828_REG_BUCK6_CTRL\t\t0x26\n+#define BD71828_REG_BUCK6_MODE\t\t0x27\n+#define BD71828_REG_BUCK6_IDLE_VOLT\t0x28\n+#define BD71828_REG_BUCK6_SUSP_VOLT\t0x29\n+#define BD71828_REG_BUCK6_VOLT\t\t0x2a\n+\n+#define BD71828_REG_BUCK7_EN\t\t0x2f\n+#define BD71828_REG_BUCK7_CTRL\t\t0x30\n+#define BD71828_REG_BUCK7_MODE\t\t0x31\n+#define BD71828_REG_BUCK7_IDLE_VOLT\t0x32\n+#define BD71828_REG_BUCK7_SUSP_VOLT\t0x33\n+#define BD71828_REG_BUCK7_VOLT\t\t0x34\n+\n+#define BD71828_REG_LDO1_EN\t\t0x39\n+#define BD71828_REG_LDO1_VOLT\t\t0x3a\n+#define BD71828_REG_LDO2_EN\t\t0x3b\n+#define BD71828_REG_LDO2_VOLT\t\t0x3c\n+#define BD71828_REG_LDO3_EN\t\t0x3d\n+#define BD71828_REG_LDO3_VOLT\t\t0x3e\n+#define BD71828_REG_LDO4_EN\t\t0x3f\n+#define BD71828_REG_LDO4_VOLT\t\t0x40\n+#define BD71828_REG_LDO5_EN\t\t0x41\n+#define BD71828_REG_LDO5_VOLT\t\t0x43\n+#define BD71828_REG_LDO5_VOLT_OPT\t0x42\n+#define BD71828_REG_LDO6_EN\t\t0x44\n+//#define BD71828_REG_LDO6_VOLT\t\t0x4\n+#define BD71828_REG_LDO7_EN\t\t0x45\n+#define BD71828_REG_LDO7_VOLT\t\t0x46\n+\n+/* GPIO */\n+\n+#define BD71828_GPIO_DRIVE_MASK\t\t0x2\n+#define BD71828_GPIO_OPEN_DRAIN\t\t0x0\n+#define BD71828_GPIO_PUSH_PULL\t\t0x2\n+#define BD71828_GPIO_OUT_HI\t\t0x1\n+#define BD71828_GPIO_OUT_LO\t\t0x0\n+#define BD71828_GPIO_OUT_MASK\t\t0x1\n+\n+#define BD71828_REG_GPIO_CTRL1\t\t0x47\n+#define BD71828_REG_GPIO_CTRL2\t\t0x48\n+#define BD71828_REG_GPIO_CTRL3\t\t0x49\n+#define BD71828_REG_IO_STAT\t\t0xed\n+\n+/* RTC */\n+#define BD71828_REG_RTC_SEC\t\t0x4c\n+#define BD71828_REG_RTC_MINUTE\t\t0x4d\n+#define BD71828_REG_RTC_HOUR\t\t0x4e\n+#define BD71828_REG_RTC_WEEK\t\t0x4f\n+#define BD71828_REG_RTC_DAY\t\t0x50\n+#define BD71828_REG_RTC_MONTH\t\t0x51\n+#define BD71828_REG_RTC_YEAR\t\t0x52\n+\n+#define BD71828_REG_RTC_ALM0_SEC\t0x53\n+#define BD71828_REG_RTC_ALM0_MINUTE\t0x54\n+#define BD71828_REG_RTC_ALM0_HOUR\t0x55\n+#define BD71828_REG_RTC_ALM0_WEEK\t0x56\n+#define BD71828_REG_RTC_ALM0_DAY\t0x57\n+#define BD71828_REG_RTC_ALM0_MONTH\t0x58\n+#define BD71828_REG_RTC_ALM0_YEAR\t0x59\n+#define BD71828_REG_RTC_ALM0_MASK\t0x61\n+\n+#define BD71828_REG_RTC_ALM1_SEC\t0x5a\n+#define BD71828_REG_RTC_ALM1_MINUTE\t0x5b\n+#define BD71828_REG_RTC_ALM1_HOUR\t0x5c\n+#define BD71828_REG_RTC_ALM1_WEEK\t0x5d\n+#define BD71828_REG_RTC_ALM1_DAY\t0x5e\n+#define BD71828_REG_RTC_ALM1_MONTH\t0x5f\n+#define BD71828_REG_RTC_ALM1_YEAR\t0x60\n+#define BD71828_REG_RTC_ALM1_MASK\t0x62\n+\n+#define BD71828_REG_RTC_ALM2\t\t0x63\n+\n+/* Charger/Battey */\n+#define BD71828_REG_CHG_STATE\t\t0x65\n+#define BD71828_REG_CHG_FULL\t\t0xd2\n+\n+/* CLK */\n+#define BD71828_REG_OUT32K\t\t0x4B\n+\n+/* LEDs */\n+#define BD71828_REG_LED_CTRL\t\t0x4A\n+#define BD71828_MASK_LED_AMBER\t\t0x80\n+#define BD71828_MASK_LED_GREEN\t\t0x40\n+#define BD71828_LED_ON\t\t\t0xff\n+#define BD71828_LED_OFF\t\t\t0x0\n+\n+/* IRQ registers */\n+#define BD71828_REG_INT_MASK_BUCK\t0xd3\n+#define BD71828_REG_INT_MASK_DCIN1\t0xd4\n+#define BD71828_REG_INT_MASK_DCIN2\t0xd5\n+#define BD71828_REG_INT_MASK_VSYS\t0xd6\n+#define BD71828_REG_INT_MASK_CHG\t0xd7\n+#define BD71828_REG_INT_MASK_BAT\t0xd8\n+#define BD71828_REG_INT_MASK_BAT_MON1\t0xd9\n+#define BD71828_REG_INT_MASK_BAT_MON2\t0xda\n+#define BD71828_REG_INT_MASK_BAT_MON3\t0xdb\n+#define BD71828_REG_INT_MASK_BAT_MON4\t0xdc\n+#define BD71828_REG_INT_MASK_TEMP\t0xdd\n+#define BD71828_REG_INT_MASK_RTC\t0xde\n+\n+\n+#define BD71828_REG_INT_MAIN\t\t0xdf\n+#define BD71828_REG_INT_BUCK\t\t0xe0\n+#define BD71828_REG_INT_DCIN1\t\t0xe1\n+#define BD71828_REG_INT_DCIN2\t\t0xe2\n+#define BD71828_REG_INT_VSYS\t\t0xe3\n+#define BD71828_REG_INT_CHG\t\t0xe4\n+#define BD71828_REG_INT_BAT\t\t0xe5\n+#define BD71828_REG_INT_BAT_MON1\t0xe6\n+#define BD71828_REG_INT_BAT_MON2\t0xe7\n+#define BD71828_REG_INT_BAT_MON3\t0xe8\n+#define BD71828_REG_INT_BAT_MON4\t0xe9\n+#define BD71828_REG_INT_TEMP\t\t0xea\n+#define BD71828_REG_INT_RTC\t\t0xeb\n+#define BD71828_REG_INT_UPDATE\t\t0xec\n+\n+#define BD71828_MAX_REGISTER BD71828_REG_IO_STAT\n+\n+/* Masks for main IRQ register bits */\n+enum {\n+\tBD71828_INT_BUCK,\n+#define BD71828_INT_BUCK_MASK BIT(BD71828_INT_BUCK)\n+\tBD71828_INT_DCIN,\n+#define BD71828_INT_DCIN_MASK BIT(BD71828_INT_DCIN)\n+\tBD71828_INT_VSYS,\n+#define BD71828_INT_VSYS_MASK BIT(BD71828_INT_VSYS)\n+\tBD71828_INT_CHG,\n+#define BD71828_INT_CHG_MASK BIT(BD71828_INT_CHG)\n+\tBD71828_INT_BAT,\n+#define BD71828_INT_BAT_MASK BIT(BD71828_INT_BAT)\n+\tBD71828_INT_BAT_MON,\n+#define BD71828_INT_BAT_MON_MASK BIT(BD71828_INT_BAT_MON)\n+\tBD71828_INT_TEMP,\n+#define BD71828_INT_TEMP_MASK BIT(BD71828_INT_TEMP)\n+\tBD71828_INT_RTC,\n+#define BD71828_INT_RTC_MASK BIT(BD71828_INT_RTC)\n+};\n+\n+/* Interrupts */\n+enum {\n+\t/* BUCK reg interrupts */\n+\tBD71828_INT_BUCK1_OCP,\n+\tBD71828_INT_BUCK2_OCP,\n+\tBD71828_INT_BUCK3_OCP,\n+\tBD71828_INT_BUCK4_OCP,\n+\tBD71828_INT_BUCK5_OCP,\n+\tBD71828_INT_BUCK6_OCP,\n+\tBD71828_INT_BUCK7_OCP,\n+\tBD71828_INT_PGFAULT,\n+\t/* DCIN1 interrupts */\n+\tBD71828_INT_DCIN_DET,\n+\tBD71828_INT_DCIN_RMV,\n+\tBD71828_INT_CLPS_OUT,\n+\tBD71828_INT_CLPS_IN,\n+\t/* DCIN2 interrupts */\n+\tBD71828_INT_DCIN_MON_RES,\n+\tBD71828_INT_DCIN_MON_DET,\n+\tBD71828_INT_LONGPUSH,\n+\tBD71828_INT_MIDPUSH,\n+\tBD71828_INT_SHORTPUSH,\n+\tBD71828_INT_PUSH,\n+\tBD71828_INT_WDOG,\n+\tBD71828_INT_SWRESET,\n+\t/* Vsys */\n+\tBD71828_INT_VSYS_UV_RES,\n+\tBD71828_INT_VSYS_UV_DET,\n+\tBD71828_INT_VSYS_LOW_RES,\n+\tBD71828_INT_VSYS_LOW_DET,\n+\tBD71828_INT_VSYS_HALL_IN,\n+\tBD71828_INT_VSYS_HALL_TOGGLE,\n+\tBD71828_INT_VSYS_MON_RES,\n+\tBD71828_INT_VSYS_MON_DET,\n+\t/* Charger */\n+\tBD71828_INT_CHG_DCIN_ILIM,\n+\tBD71828_INT_CHG_TOPOFF_TO_DONE,\n+\tBD71828_INT_CHG_WDG_TEMP,\n+\tBD71828_INT_CHG_WDG_TIME,\n+\tBD71828_INT_CHG_RECHARGE_RES,\n+\tBD71828_INT_CHG_RECHARGE_DET,\n+\tBD71828_INT_CHG_RANGED_TEMP_TRANSITION,\n+\tBD71828_INT_CHG_STATE_TRANSITION,\n+\t/* Battery */\n+\tBD71828_INT_BAT_TEMP_NORMAL,\n+\tBD71828_INT_BAT_TEMP_ERANGE,\n+\tBD71828_INT_BAT_TEMP_WARN,\n+\tBD71828_INT_BAT_REMOVED,\n+\tBD71828_INT_BAT_DETECTED,\n+\tBD71828_INT_THERM_REMOVED,\n+\tBD71828_INT_THERM_DETECTED,\n+\t/* Battery Mon 1 */\n+\tBD71828_INT_BAT_DEAD,\n+\tBD71828_INT_BAT_SHORTC_RES,\n+\tBD71828_INT_BAT_SHORTC_DET,\n+\tBD71828_INT_BAT_LOW_VOLT_RES,\n+\tBD71828_INT_BAT_LOW_VOLT_DET,\n+\tBD71828_INT_BAT_OVER_VOLT_RES,\n+\tBD71828_INT_BAT_OVER_VOLT_DET,\n+\t/* Battery Mon 2 */\n+\tBD71828_INT_BAT_MON_RES,\n+\tBD71828_INT_BAT_MON_DET,\n+\t/* Battery Mon 3 (Coulomb counter) */\n+\tBD71828_INT_BAT_CC_MON1,\n+\tBD71828_INT_BAT_CC_MON2,\n+\tBD71828_INT_BAT_CC_MON3,\n+\t/* Battery Mon 4 */\n+\tBD71828_INT_BAT_OVER_CURR_1_RES,\n+\tBD71828_INT_BAT_OVER_CURR_1_DET,\n+\tBD71828_INT_BAT_OVER_CURR_2_RES,\n+\tBD71828_INT_BAT_OVER_CURR_2_DET,\n+\tBD71828_INT_BAT_OVER_CURR_3_RES,\n+\tBD71828_INT_BAT_OVER_CURR_3_DET,\n+\t/* Temperature */\n+\tBD71828_INT_TEMP_BAT_LOW_RES,\n+\tBD71828_INT_TEMP_BAT_LOW_DET,\n+\tBD71828_INT_TEMP_BAT_HI_RES,\n+\tBD71828_INT_TEMP_BAT_HI_DET,\n+\tBD71828_INT_TEMP_CHIP_OVER_125_RES,\n+\tBD71828_INT_TEMP_CHIP_OVER_125_DET,\n+\tBD71828_INT_TEMP_CHIP_OVER_VF_DET,\n+\tBD71828_INT_TEMP_CHIP_OVER_VF_RES,\n+\t/* RTC Alarm */\n+\tBD71828_INT_RTC0,\n+\tBD71828_INT_RTC1,\n+\tBD71828_INT_RTC2,\n+};\n+\n+#define BD71828_INT_BUCK1_OCP_MASK\t\t\t0x1\n+#define BD71828_INT_BUCK2_OCP_MASK\t\t\t0x2\n+#define BD71828_INT_BUCK3_OCP_MASK\t\t\t0x4\n+#define BD71828_INT_BUCK4_OCP_MASK\t\t\t0x8\n+#define BD71828_INT_BUCK5_OCP_MASK\t\t\t0x10\n+#define BD71828_INT_BUCK6_OCP_MASK\t\t\t0x20\n+#define BD71828_INT_BUCK7_OCP_MASK\t\t\t0x40\n+#define BD71828_INT_PGFAULT_MASK\t\t\t0x80\n+\n+#define BD71828_INT_DCIN_DET_MASK\t\t\t0x1\n+#define BD71828_INT_DCIN_RMV_MASK\t\t\t0x2\n+#define BD71828_INT_CLPS_OUT_MASK\t\t\t0x4\n+#define BD71828_INT_CLPS_IN_MASK\t\t\t0x8\n+\t/* DCIN2 interrupts */\n+#define BD71828_INT_DCIN_MON_RES_MASK\t\t\t0x1\n+#define BD71828_INT_DCIN_MON_DET_MASK\t\t\t0x2\n+#define BD71828_INT_LONGPUSH_MASK\t\t\t0x4\n+#define BD71828_INT_MIDPUSH_MASK\t\t\t0x8\n+#define BD71828_INT_SHORTPUSH_MASK\t\t\t0x10\n+#define BD71828_INT_PUSH_MASK\t\t\t\t0x20\n+#define BD71828_INT_WDOG_MASK\t\t\t\t0x40\n+#define BD71828_INT_SWRESET_MASK\t\t\t0x80\n+\t/* Vsys */\n+#define BD71828_INT_VSYS_UV_RES_MASK\t\t\t0x1\n+#define BD71828_INT_VSYS_UV_DET_MASK\t\t\t0x2\n+#define BD71828_INT_VSYS_LOW_RES_MASK\t\t\t0x4\n+#define BD71828_INT_VSYS_LOW_DET_MASK\t\t\t0x8\n+#define BD71828_INT_VSYS_HALL_IN_MASK\t\t\t0x10\n+#define BD71828_INT_VSYS_HALL_TOGGLE_MASK\t\t0x20\n+#define BD71828_INT_VSYS_MON_RES_MASK\t\t\t0x40\n+#define BD71828_INT_VSYS_MON_DET_MASK\t\t\t0x80\n+\t/* Charger */\n+#define BD71828_INT_CHG_DCIN_ILIM_MASK\t\t\t0x1\n+#define BD71828_INT_CHG_TOPOFF_TO_DONE_MASK\t\t0x2\n+#define BD71828_INT_CHG_WDG_TEMP_MASK\t\t\t0x4\n+#define BD71828_INT_CHG_WDG_TIME_MASK\t\t\t0x8\n+#define BD71828_INT_CHG_RECHARGE_RES_MASK\t\t0x10\n+#define BD71828_INT_CHG_RECHARGE_DET_MASK\t\t0x20\n+#define BD71828_INT_CHG_RANGED_TEMP_TRANSITION_MASK\t0x40\n+#define BD71828_INT_CHG_STATE_TRANSITION_MASK\t\t0x80\n+\t/* Battery */\n+#define BD71828_INT_BAT_TEMP_NORMAL_MASK\t\t0x1\n+#define BD71828_INT_BAT_TEMP_ERANGE_MASK\t\t0x2\n+#define BD71828_INT_BAT_TEMP_WARN_MASK\t\t\t0x4\n+#define BD71828_INT_BAT_REMOVED_MASK\t\t\t0x10\n+#define BD71828_INT_BAT_DETECTED_MASK\t\t\t0x20\n+#define BD71828_INT_THERM_REMOVED_MASK\t\t\t0x40\n+#define BD71828_INT_THERM_DETECTED_MASK\t\t\t0x80\n+\t/* Battery Mon 1 */\n+#define BD71828_INT_BAT_DEAD_MASK\t\t\t0x2\n+#define BD71828_INT_BAT_SHORTC_RES_MASK\t\t\t0x4\n+#define BD71828_INT_BAT_SHORTC_DET_MASK\t\t\t0x8\n+#define BD71828_INT_BAT_LOW_VOLT_RES_MASK\t\t0x10\n+#define BD71828_INT_BAT_LOW_VOLT_DET_MASK\t\t0x20\n+#define BD71828_INT_BAT_OVER_VOLT_RES_MASK\t\t0x40\n+#define BD71828_INT_BAT_OVER_VOLT_DET_MASK\t\t0x80\n+\t/* Battery Mon 2 */\n+#define BD71828_INT_BAT_MON_RES_MASK\t\t\t0x1\n+#define BD71828_INT_BAT_MON_DET_MASK\t\t\t0x2\n+\t/* Battery Mon 3 (Coulomb counter) */\n+#define BD71828_INT_BAT_CC_MON1_MASK\t\t\t0x1\n+#define BD71828_INT_BAT_CC_MON2_MASK\t\t\t0x2\n+#define BD71828_INT_BAT_CC_MON3_MASK\t\t\t0x4\n+\t/* Battery Mon 4 */\n+#define BD71828_INT_BAT_OVER_CURR_1_RES_MASK\t\t0x1\n+#define BD71828_INT_BAT_OVER_CURR_1_DET_MASK\t\t0x2\n+#define BD71828_INT_BAT_OVER_CURR_2_RES_MASK\t\t0x4\n+#define BD71828_INT_BAT_OVER_CURR_2_DET_MASK\t\t0x8\n+#define BD71828_INT_BAT_OVER_CURR_3_RES_MASK\t\t0x10\n+#define BD71828_INT_BAT_OVER_CURR_3_DET_MASK\t\t0x20\n+\t/* Temperature */\n+#define BD71828_INT_TEMP_BAT_LOW_RES_MASK\t\t0x1\n+#define BD71828_INT_TEMP_BAT_LOW_DET_MASK\t\t0x2\n+#define BD71828_INT_TEMP_BAT_HI_RES_MASK\t\t0x4\n+#define BD71828_INT_TEMP_BAT_HI_DET_MASK\t\t0x8\n+#define BD71828_INT_TEMP_CHIP_OVER_125_RES_MASK\t\t0x10\n+#define BD71828_INT_TEMP_CHIP_OVER_125_DET_MASK\t\t0x20\n+#define BD71828_INT_TEMP_CHIP_OVER_VF_RES_MASK\t\t0x40\n+#define BD71828_INT_TEMP_CHIP_OVER_VF_DET_MASK\t\t0x80\n+\t/* RTC Alarm */\n+#define BD71828_INT_RTC0_MASK\t\t\t\t0x1\n+#define BD71828_INT_RTC1_MASK\t\t\t\t0x2\n+#define BD71828_INT_RTC2_MASK\t\t\t\t0x4\n+\n+#define BD71828_OUT32K_EN\t\t\t\t0x1\n+#define BD71828_OUT_TYPE_MASK\t\t\t\t0x2\n+#define BD71828_OUT_TYPE_OPEN_DRAIN\t\t\t0x0\n+#define BD71828_OUT_TYPE_CMOS\t\t\t\t0x2\n+\n+#endif /* __LINUX_MFD_BD71828_H__ */\ndiff --git a/include/linux/mfd/rohm-generic.h b/include/linux/mfd/rohm-generic.h\nindex 922f88008232..ff3dd7578fd3 100644\n--- a/include/linux/mfd/rohm-generic.h\n+++ b/include/linux/mfd/rohm-generic.h\n@@ -8,6 +8,7 @@ enum rohm_chip_type {\n \tROHM_CHIP_TYPE_BD71837 = 0,\n \tROHM_CHIP_TYPE_BD71847,\n \tROHM_CHIP_TYPE_BD70528,\n+\tROHM_CHIP_TYPE_BD71828,\n \tROHM_CHIP_TYPE_AMOUNT\n };\n \n", "prefixes": [ "v7", "05/12" ] }