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[2/3,SRU,U/OEM-5.13] perf/x86/intel: Add more events requires FRONTEND MSR on Sapphire Rapids

Message ID 20210713043655.2299851-3-vicamo.yang@canonical.com
State Accepted
Headers show
Series Fix broken PMU hardware on ADL | expand

Commit Message

You-Sheng Yang July 13, 2021, 4:36 a.m. UTC
From: Kan Liang <kan.liang@linux.intel.com>

BugLink: https://bugs.launchpad.net/bugs/1933617

On Sapphire Rapids, there are two more events 0x40ad and 0x04c2 which
rely on the FRONTEND MSR. If the FRONTEND MSR is not set correctly, the
count value is not correct.

Update intel_spr_extra_regs[] to support them.

Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/1624029174-122219-3-git-send-email-kan.liang@linux.intel.com
(cherry picked from commit d18216fafecf2a3a7c2b97086892269d6ab3cd5e)
Signed-off-by: You-Sheng Yang <vicamo.yang@canonical.com>
---
 arch/x86/events/intel/core.c | 2 ++
 1 file changed, 2 insertions(+)
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Patch

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 83c8dba7b4b8..93b6198af4c1 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -280,6 +280,8 @@  static struct extra_reg intel_spr_extra_regs[] __read_mostly = {
 	INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
 	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 	INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
+	INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
+	INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
 	EVENT_EXTRA_END
 };