| Message ID | 20191121081538.3443236-2-vicamo.yang@canonical.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add perf support for Comet Lake/Ice Lake CPU | expand |
On Thu, Nov 21, 2019 at 04:15:33PM +0800, You-Sheng Yang wrote: > From: Peter Zijlstra <peterz@infradead.org> > > BugLink: https://bugs.launchpad.net/bugs/1848978 > > Icelake extended the general counters to 8, even when SMT is enabled. > However only a (large) subset of the events can be used on all 8 > counters. > > The events that can or cannot be used on all counters are organized > in ranges. > > A lot of scheduler constraints are required to handle all this. > > To avoid blowing up the tables add event code ranges to the constraint > tables, and a new inline function to match them. > > Originally-by: Andi Kleen <ak@linux.intel.com> > Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> # developer hat on > Signed-off-by: Kan Liang <kan.liang@linux.intel.com> > Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> # maintainer hat on > Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> > Cc: Arnaldo Carvalho de Melo <acme@redhat.com> > Cc: Jiri Olsa <jolsa@redhat.com> > Cc: Linus Torvalds <torvalds@linux-foundation.org> > Cc: Peter Zijlstra <peterz@infradead.org> > Cc: Stephane Eranian <eranian@google.com> > Cc: Thomas Gleixner <tglx@linutronix.de> > Cc: Vince Weaver <vincent.weaver@maine.edu> > Cc: acme@kernel.org > Cc: jolsa@kernel.org > Link: https://lkml.kernel.org/r/20190402194509.2832-8-kan.liang@linux.intel.com > Signed-off-by: Ingo Molnar <mingo@kernel.org> > (backported from commit 63b79f6ebc464afb730bc45762c820795e276da1) > Signed-off-by: You-Sheng Yang <vicamo.yang@canonical.com> > --- > arch/x86/events/perf_event.h | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h > index 8751008fc170..6d144f6e9573 100644 > --- a/arch/x86/events/perf_event.h > +++ b/arch/x86/events/perf_event.h > @@ -381,6 +381,9 @@ struct cpu_hw_events { > #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ > EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) > > +#define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ > + EVENT_CONSTRAINT_RANGE(c, e, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) > + > /* Check only flags, but allow all event/umask */ > #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ > EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS) This patch looks weird, you are defining INTEL_FLAGS_EVENT_CONSTRAINT_RANGE again by reverting 6b89d4c1a. Thanks, Anthony
On 2019-11-26 22:40, Anthony Wong wrote: > On Thu, Nov 21, 2019 at 04:15:33PM +0800, You-Sheng Yang wrote: >> From: Peter Zijlstra <peterz@infradead.org> >> >> BugLink: https://bugs.launchpad.net/bugs/1848978 >> >> Icelake extended the general counters to 8, even when SMT is enabled. >> However only a (large) subset of the events can be used on all 8 >> counters. >> >> The events that can or cannot be used on all counters are organized >> in ranges. >> >> A lot of scheduler constraints are required to handle all this. >> >> To avoid blowing up the tables add event code ranges to the constraint >> tables, and a new inline function to match them. >> >> Originally-by: Andi Kleen <ak@linux.intel.com> >> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> # developer hat on >> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> >> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> # maintainer hat on >> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> >> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> >> Cc: Jiri Olsa <jolsa@redhat.com> >> Cc: Linus Torvalds <torvalds@linux-foundation.org> >> Cc: Peter Zijlstra <peterz@infradead.org> >> Cc: Stephane Eranian <eranian@google.com> >> Cc: Thomas Gleixner <tglx@linutronix.de> >> Cc: Vince Weaver <vincent.weaver@maine.edu> >> Cc: acme@kernel.org >> Cc: jolsa@kernel.org >> Link: https://lkml.kernel.org/r/20190402194509.2832-8-kan.liang@linux.intel.com >> Signed-off-by: Ingo Molnar <mingo@kernel.org> >> (backported from commit 63b79f6ebc464afb730bc45762c820795e276da1) >> Signed-off-by: You-Sheng Yang <vicamo.yang@canonical.com> >> --- >> arch/x86/events/perf_event.h | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h >> index 8751008fc170..6d144f6e9573 100644 >> --- a/arch/x86/events/perf_event.h >> +++ b/arch/x86/events/perf_event.h >> @@ -381,6 +381,9 @@ struct cpu_hw_events { >> #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ >> EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) >> >> +#define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ >> + EVENT_CONSTRAINT_RANGE(c, e, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) >> + >> /* Check only flags, but allow all event/umask */ >> #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ >> EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS) > > This patch looks weird, you are defining INTEL_FLAGS_EVENT_CONSTRAINT_RANGE > again by reverting 6b89d4c1a. Thank you. I'll drop this patch from patchset for Eoan, and add 6b89d4c1a to D/OEM-OSP1-B to address that bug. > Thanks, > Anthony >
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 8751008fc170..6d144f6e9573 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -381,6 +381,9 @@ struct cpu_hw_events { #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS) +#define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \ + EVENT_CONSTRAINT_RANGE(c, e, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS) + /* Check only flags, but allow all event/umask */ #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \ EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)