diff mbox

UBUNTU: SAUCE: pinctrl/amd: Remove the default de-bounce time

Message ID 1470882185-25261-2-git-send-email-alex.hung@canonical.com
State New
Headers show

Commit Message

Alex Hung Aug. 11, 2016, 2:23 a.m. UTC 
From: Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com>

In the function amd_gpio_irq_enable and amd_gpio_direction_input, remove the code which is setting the default de-bounce time to 2.75ms.

The driver code shall use the same settings as specified in BIOS.
Any default assignment impacts TouchPad behaviour when the LevelTrig is set to EDGE FALLING.

The original patch: http://www.spinics.net/lists/stable/msg139761.html

BugLink: http://bugs.launchpad.net/bugs/1612006

Reviewed-by: Ken Xue <Ken.Xue@amd.com>
Signed-off-by: Nitesh Kumar Agrawal <Nitesh-kumar.Agrawal@amd.com>
Signed-off-by: Alex Hung <alex.hung@canonical.com>
---
 drivers/pinctrl/pinctrl-amd.c | 20 +-------------------
 1 file changed, 1 insertion(+), 19 deletions(-)

Comments

Stefan Bader Aug. 11, 2016, 2:19 p.m. UTC | #1 
I hope not setting the debounce time is always ok (not sure how much hw is using
that driver). Not really happy about a change like that...
Tim Gardner Aug. 11, 2016, 3:19 p.m. UTC | #2 
I'm kind of underwhelmed by the lack of upstream review, but at least
this only impacts a limited range of devices.
Stefan Bader Aug. 12, 2016, 4:38 a.m. UTC | #3
diff mbox

Patch

diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
index 3318f1d..3cacfa4 100644
--- a/drivers/pinctrl/pinctrl-amd.c
+++ b/drivers/pinctrl/pinctrl-amd.c
@@ -48,16 +48,6 @@  static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
 
 	spin_lock_irqsave(&gpio_dev->lock, flags);
 	pin_reg = readl(gpio_dev->base + offset * 4);
-	/*
-	 * Suppose BIOS or Bootloader sets specific debounce for the
-	 * GPIO. if not, set debounce to be  2.75ms and remove glitch.
-	*/
-	if ((pin_reg & DB_TMR_OUT_MASK) == 0) {
-		pin_reg |= 0xf;
-		pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
-		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
-		pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
-	}
 
 	pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
 	writel(pin_reg, gpio_dev->base + offset * 4);
@@ -331,15 +321,7 @@  static void amd_gpio_irq_enable(struct irq_data *d)
 
 	spin_lock_irqsave(&gpio_dev->lock, flags);
 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
-	/*
-		Suppose BIOS or Bootloader sets specific debounce for the
-		GPIO. if not, set debounce to be  2.75ms.
-	*/
-	if ((pin_reg & DB_TMR_OUT_MASK) == 0) {
-		pin_reg |= 0xf;
-		pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
-		pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
-	}
+
 	pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
 	pin_reg |= BIT(INTERRUPT_MASK_OFF);
 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);