| Message ID | 20210127061003.605350-1-koba.ko@canonical.com |
|---|---|
| Headers | show |
| Series | UBUNTU: SAUCE: Fix the video can't output through WD19TB connected on TGL's Type-C port during cold-boot | expand |
On 27.01.21 07:10, Koba Ko wrote: > BugLink: https://bugs.launchpad.net/bugs/1913372 > > [Impact] > WD19TB would report the number of lane(2-lane) and it works well on Type-C port > of TGL platform. Change the LTTPR mode to non-transparent mode, WD19TB would > report the larger number of lane(4-lane). It's over the type-c port's bandwidth. > > [Fix] > The patch is provided by Imre(https://patchwork.freedesktop.org/series/86267/). > Calculate the PBN divider value based on the rate and lane count link parameters > that the driver uses for all other computation. > > [Test Case] > 1. Connected the WD19TB with the TGL platform's Type-C port and > connected the external monitor on WD19TB with HDMI/Displayport. > 2. Cold boot the TGL platform. > 3. Check the monitor can be blinked and the video can output to the monitor. > > [Where problems could occur] > It's correct to calculate the PBN divider based on the source's rate > and lane count, not the mst's capability. > > Imre Deak (2): > drm/dp/mst: Export drm_dp_get_vc_payload_bw() > drm/i915: Fix the MST PBN divider calculation > > drivers/gpu/drm/drm_dp_mst_topology.c | 24 +++++++++++++++------ > drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +++- > include/drm/drm_dp_mst_helper.h | 1 + > 3 files changed, 22 insertions(+), 7 deletions(-) > Non-upstream changes to i915 for stable kernels is like volunteering to test-drive the new SM studio...
On Wed, Jan 27, 2021 at 02:10:01PM +0800, Koba Ko wrote:
> BugLink: https://bugs.launchpad.net/bugs/1913372
Recently posted, and no review yet upstream - i'll wait a bit before applying
it for H.
On Wed, Jan 27, 2021 at 02:10:01PM +0800, Koba Ko wrote:
> BugLink: https://bugs.launchpad.net/bugs/1913372
Dropped your patches, instead cherry-picked the corresponding commits from
linux-next into H:
a321fc2b4e60 drm/dp/mst: Export drm_dp_get_vc_payload_bw()
b59c27cab257 drm/i915: Fix the MST PBN divider calculation
On Fri, Feb 05, 2021 at 12:14:05PM +0100, Paolo Pisati wrote: > On Wed, Jan 27, 2021 at 02:10:01PM +0800, Koba Ko wrote: > > BugLink: https://bugs.launchpad.net/bugs/1913372 > > Dropped your patches, instead cherry-picked the corresponding commits from > linux-next into H: > > a321fc2b4e60 drm/dp/mst: Export drm_dp_get_vc_payload_bw() > b59c27cab257 drm/i915: Fix the MST PBN divider calculation I've done the same to unstable/5.11 (cherry-picked the same commits from linux-next). Thanks, -Andrea
On 05.02.21 12:14, Paolo Pisati wrote: > On Wed, Jan 27, 2021 at 02:10:01PM +0800, Koba Ko wrote: >> BugLink: https://bugs.launchpad.net/bugs/1913372 > > Dropped your patches, instead cherry-picked the corresponding commits from > linux-next into H: > > a321fc2b4e60 drm/dp/mst: Export drm_dp_get_vc_payload_bw() > b59c27cab257 drm/i915: Fix the MST PBN divider calculation > Did you add the BugLink when cherry picking? Which IMO would be a better way of doing this (it is the same patches, just now more upstream than before). So instead of NAKing I'd say APPLIED/Cmnt here. Feels to better reflect the reality. -Stefan
On 27.01.21 07:10, Koba Ko wrote: > BugLink: https://bugs.launchpad.net/bugs/1913372 > > [Impact] > WD19TB would report the number of lane(2-lane) and it works well on Type-C port > of TGL platform. Change the LTTPR mode to non-transparent mode, WD19TB would > report the larger number of lane(4-lane). It's over the type-c port's bandwidth. > > [Fix] > The patch is provided by Imre(https://patchwork.freedesktop.org/series/86267/). > Calculate the PBN divider value based on the rate and lane count link parameters > that the driver uses for all other computation. > > [Test Case] > 1. Connected the WD19TB with the TGL platform's Type-C port and > connected the external monitor on WD19TB with HDMI/Displayport. > 2. Cold boot the TGL platform. > 3. Check the monitor can be blinked and the video can output to the monitor. > > [Where problems could occur] > It's correct to calculate the PBN divider based on the source's rate > and lane count, not the mst's capability. > > Imre Deak (2): > drm/dp/mst: Export drm_dp_get_vc_payload_bw() > drm/i915: Fix the MST PBN divider calculation > > drivers/gpu/drm/drm_dp_mst_topology.c | 24 +++++++++++++++------ > drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +++- > include/drm/drm_dp_mst_helper.h | 1 + > 3 files changed, 22 insertions(+), 7 deletions(-) > As Paolo reported those patches are now in linux-next. So when picking into G/F we should prefer those (assumed identical) versions and just move BugLink and s-o-b's ahead. At time of application we probably should even double-check whether things have moved into the main kernel repo already. a321fc2b4e60 drm/dp/mst: Export drm_dp_get_vc_payload_bw() b59c27cab257 drm/i915: Fix the MST PBN divider calculation Acked-by: Stefan Bader <stefan.bader@canonical.com>
On 27.01.21 07:10, Koba Ko wrote: > BugLink: https://bugs.launchpad.net/bugs/1913372 > > [Impact] > WD19TB would report the number of lane(2-lane) and it works well on Type-C port > of TGL platform. Change the LTTPR mode to non-transparent mode, WD19TB would > report the larger number of lane(4-lane). It's over the type-c port's bandwidth. > > [Fix] > The patch is provided by Imre(https://patchwork.freedesktop.org/series/86267/). > Calculate the PBN divider value based on the rate and lane count link parameters > that the driver uses for all other computation. > > [Test Case] > 1. Connected the WD19TB with the TGL platform's Type-C port and > connected the external monitor on WD19TB with HDMI/Displayport. > 2. Cold boot the TGL platform. > 3. Check the monitor can be blinked and the video can output to the monitor. > > [Where problems could occur] > It's correct to calculate the PBN divider based on the source's rate > and lane count, not the mst's capability. > > Imre Deak (2): > drm/dp/mst: Export drm_dp_get_vc_payload_bw() > drm/i915: Fix the MST PBN divider calculation > > drivers/gpu/drm/drm_dp_mst_topology.c | 24 +++++++++++++++------ > drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +++- > include/drm/drm_dp_mst_helper.h | 1 + > 3 files changed, 22 insertions(+), 7 deletions(-) > With Stefan's comments addressed: Acked-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
On 27.01.21 07:10, Koba Ko wrote: > BugLink: https://bugs.launchpad.net/bugs/1913372 > > [Impact] > WD19TB would report the number of lane(2-lane) and it works well on Type-C port > of TGL platform. Change the LTTPR mode to non-transparent mode, WD19TB would > report the larger number of lane(4-lane). It's over the type-c port's bandwidth. > > [Fix] > The patch is provided by Imre(https://patchwork.freedesktop.org/series/86267/). > Calculate the PBN divider value based on the rate and lane count link parameters > that the driver uses for all other computation. > > [Test Case] > 1. Connected the WD19TB with the TGL platform's Type-C port and > connected the external monitor on WD19TB with HDMI/Displayport. > 2. Cold boot the TGL platform. > 3. Check the monitor can be blinked and the video can output to the monitor. > > [Where problems could occur] > It's correct to calculate the PBN divider based on the source's rate > and lane count, not the mst's capability. > > Imre Deak (2): > drm/dp/mst: Export drm_dp_get_vc_payload_bw() > drm/i915: Fix the MST PBN divider calculation > > drivers/gpu/drm/drm_dp_mst_topology.c | 24 +++++++++++++++------ > drivers/gpu/drm/i915/display/intel_dp_mst.c | 4 +++- > include/drm/drm_dp_mst_helper.h | 1 + > 3 files changed, 22 insertions(+), 7 deletions(-) > Applied to groovy:linux/master-next. Both patches are now upstream and I picked those instead of the provided SAUCE patches. However patch #1 does not apply at all to focal. If you still think it should go into Focal/5.4, please re-submit the upstream patches backported to Focal. -Stefan