| Message ID | 20191127080028.200261-1-vicamo.yang@canonical.com |
|---|---|
| Headers | show |
| Series | Add perf support for Comet Lake/Ice Lake CPU | expand |
On Wed, Nov 27, 2019 at 04:00:08PM +0800, You-Sheng Yang wrote: > BugLink: https://bugs.launchpad.net/bugs/1848978 > > [Impact] > There is no complete perf support for Comet Lake CPU. For Ice Lake, some > changes has been included in v5.3, but still misses CPU IDs. > > [Fix] > perf support for Comet Lake is based on previous works for Ice Lake, so > changes for both have to be backported. > > [Test Case] > On platforms with Comet Lake/Ice Lake CPUs, one should find new > cstate_pkg events c{8,9,10}-residency appear in output of `perf list` > for use. > > [Regression Potential] > Low. This backports perf support for previously incompletedly supported > cpu models. > > V2: > - add one more patch from commit 6b89d4c1ae85 ("perf/x86/intel: Fix > INTEL_FLAGS_EVENT_CONSTRAINT* masking"). > > Andi Kleen (3): > perf/x86/kvm: Avoid unnecessary work in guest filtering > perf/x86/intel: Extract memory code PEBS parser for reuse > perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles them > > Kan Liang (14): > x86/cpufeature: Add facility to check for min microcode revisions > perf/x86: Support outputting XMM registers > perf/x86/intel/ds: Extract code of event update in short period > perf/x86/intel: Support adaptive PEBS v4 > perf/x86/intel: Add Icelake support > perf/x86/intel/uncore: Add Intel Icelake uncore support > perf/x86/intel: Add Icelake desktop CPUID > perf/x86/intel: Add more Icelake CPUIDs > x86/cpu: Add Comet Lake to the Intel CPU models header > perf/x86/intel: Add Comet Lake CPU support > perf/x86/msr: Add Comet Lake CPU support > perf/x86/cstate: Add Comet Lake CPU support > perf/x86/msr: Add new CPU model numbers for Ice Lake > perf/x86/cstate: Update C-state counters for Ice Lake > > Peter Zijlstra (1): > perf/x86: Support constraint ranges > > Rajneesh Bhardwaj (1): > perf/x86: Add Intel Ice Lake NNPI uncore support > > Stephane Eranian (1): > perf/x86/intel: Fix INTEL_FLAGS_EVENT_CONSTRAINT* masking > > arch/x86/events/core.c | 15 + > arch/x86/events/intel/core.c | 207 ++++++++++- > arch/x86/events/intel/cstate.c | 41 ++- > arch/x86/events/intel/ds.c | 505 ++++++++++++++++++++++---- > arch/x86/events/intel/lbr.c | 35 +- > arch/x86/events/intel/rapl.c | 1 + > arch/x86/events/intel/uncore.c | 8 + > arch/x86/events/intel/uncore.h | 1 + > arch/x86/events/intel/uncore_snb.c | 91 +++++ > arch/x86/events/msr.c | 5 + > arch/x86/events/perf_event.h | 94 ++++- > arch/x86/include/asm/cpu_device_id.h | 28 ++ > arch/x86/include/asm/intel-family.h | 3 + > arch/x86/include/asm/intel_ds.h | 2 +- > arch/x86/include/asm/msr-index.h | 1 + > arch/x86/include/asm/perf_event.h | 50 ++- > arch/x86/include/uapi/asm/perf_regs.h | 23 +- > arch/x86/kernel/cpu/match.c | 31 ++ > arch/x86/kernel/perf_regs.c | 27 +- > 19 files changed, 1049 insertions(+), 119 deletions(-) Good for oem-osp1, this patchset is needed there for OEM projects. BugLinks are missing in the patches though, which should be: BugLink: https://bugs.launchpad.net/bugs/1848978 Acked-by: Anthony Wong <anthony.wong@canonical.com>
On 27.11.19 09:00, You-Sheng Yang wrote: > BugLink: https://bugs.launchpad.net/bugs/1848978 > > [Impact] > There is no complete perf support for Comet Lake CPU. For Ice Lake, some > changes has been included in v5.3, but still misses CPU IDs. > > [Fix] > perf support for Comet Lake is based on previous works for Ice Lake, so > changes for both have to be backported. > > [Test Case] > On platforms with Comet Lake/Ice Lake CPUs, one should find new > cstate_pkg events c{8,9,10}-residency appear in output of `perf list` > for use. > > [Regression Potential] > Low. This backports perf support for previously incompletedly supported > cpu models. > > V2: > - add one more patch from commit 6b89d4c1ae85 ("perf/x86/intel: Fix > INTEL_FLAGS_EVENT_CONSTRAINT* masking"). > > Andi Kleen (3): > perf/x86/kvm: Avoid unnecessary work in guest filtering > perf/x86/intel: Extract memory code PEBS parser for reuse > perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles them > > Kan Liang (14): > x86/cpufeature: Add facility to check for min microcode revisions > perf/x86: Support outputting XMM registers > perf/x86/intel/ds: Extract code of event update in short period > perf/x86/intel: Support adaptive PEBS v4 > perf/x86/intel: Add Icelake support > perf/x86/intel/uncore: Add Intel Icelake uncore support > perf/x86/intel: Add Icelake desktop CPUID > perf/x86/intel: Add more Icelake CPUIDs > x86/cpu: Add Comet Lake to the Intel CPU models header > perf/x86/intel: Add Comet Lake CPU support > perf/x86/msr: Add Comet Lake CPU support > perf/x86/cstate: Add Comet Lake CPU support > perf/x86/msr: Add new CPU model numbers for Ice Lake > perf/x86/cstate: Update C-state counters for Ice Lake > > Peter Zijlstra (1): > perf/x86: Support constraint ranges > > Rajneesh Bhardwaj (1): > perf/x86: Add Intel Ice Lake NNPI uncore support > > Stephane Eranian (1): > perf/x86/intel: Fix INTEL_FLAGS_EVENT_CONSTRAINT* masking > > arch/x86/events/core.c | 15 + > arch/x86/events/intel/core.c | 207 ++++++++++- > arch/x86/events/intel/cstate.c | 41 ++- > arch/x86/events/intel/ds.c | 505 ++++++++++++++++++++++---- > arch/x86/events/intel/lbr.c | 35 +- > arch/x86/events/intel/rapl.c | 1 + > arch/x86/events/intel/uncore.c | 8 + > arch/x86/events/intel/uncore.h | 1 + > arch/x86/events/intel/uncore_snb.c | 91 +++++ > arch/x86/events/msr.c | 5 + > arch/x86/events/perf_event.h | 94 ++++- > arch/x86/include/asm/cpu_device_id.h | 28 ++ > arch/x86/include/asm/intel-family.h | 3 + > arch/x86/include/asm/intel_ds.h | 2 +- > arch/x86/include/asm/msr-index.h | 1 + > arch/x86/include/asm/perf_event.h | 50 ++- > arch/x86/include/uapi/asm/perf_regs.h | 23 +- > arch/x86/kernel/cpu/match.c | 31 ++ > arch/x86/kernel/perf_regs.c | 27 +- > 19 files changed, 1049 insertions(+), 119 deletions(-) > Disco goes EOL in January. It makes no sense to add a lot of change for new features to it. Even smaller feature additions are probably pointless. -Stefan
On 27.11.2019 10.00, You-Sheng Yang wrote: > BugLink: https://bugs.launchpad.net/bugs/1848978 > > [Impact] > There is no complete perf support for Comet Lake CPU. For Ice Lake, some > changes has been included in v5.3, but still misses CPU IDs. > > [Fix] > perf support for Comet Lake is based on previous works for Ice Lake, so > changes for both have to be backported. > > [Test Case] > On platforms with Comet Lake/Ice Lake CPUs, one should find new > cstate_pkg events c{8,9,10}-residency appear in output of `perf list` > for use. > > [Regression Potential] > Low. This backports perf support for previously incompletedly supported > cpu models. > > V2: > - add one more patch from commit 6b89d4c1ae85 ("perf/x86/intel: Fix > INTEL_FLAGS_EVENT_CONSTRAINT* masking"). > > Andi Kleen (3): > perf/x86/kvm: Avoid unnecessary work in guest filtering > perf/x86/intel: Extract memory code PEBS parser for reuse > perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles them > > Kan Liang (14): > x86/cpufeature: Add facility to check for min microcode revisions > perf/x86: Support outputting XMM registers > perf/x86/intel/ds: Extract code of event update in short period > perf/x86/intel: Support adaptive PEBS v4 > perf/x86/intel: Add Icelake support > perf/x86/intel/uncore: Add Intel Icelake uncore support > perf/x86/intel: Add Icelake desktop CPUID > perf/x86/intel: Add more Icelake CPUIDs > x86/cpu: Add Comet Lake to the Intel CPU models header > perf/x86/intel: Add Comet Lake CPU support > perf/x86/msr: Add Comet Lake CPU support > perf/x86/cstate: Add Comet Lake CPU support > perf/x86/msr: Add new CPU model numbers for Ice Lake > perf/x86/cstate: Update C-state counters for Ice Lake > > Peter Zijlstra (1): > perf/x86: Support constraint ranges > > Rajneesh Bhardwaj (1): > perf/x86: Add Intel Ice Lake NNPI uncore support > > Stephane Eranian (1): > perf/x86/intel: Fix INTEL_FLAGS_EVENT_CONSTRAINT* masking > > arch/x86/events/core.c | 15 + > arch/x86/events/intel/core.c | 207 ++++++++++- > arch/x86/events/intel/cstate.c | 41 ++- > arch/x86/events/intel/ds.c | 505 ++++++++++++++++++++++---- > arch/x86/events/intel/lbr.c | 35 +- > arch/x86/events/intel/rapl.c | 1 + > arch/x86/events/intel/uncore.c | 8 + > arch/x86/events/intel/uncore.h | 1 + > arch/x86/events/intel/uncore_snb.c | 91 +++++ > arch/x86/events/msr.c | 5 + > arch/x86/events/perf_event.h | 94 ++++- > arch/x86/include/asm/cpu_device_id.h | 28 ++ > arch/x86/include/asm/intel-family.h | 3 + > arch/x86/include/asm/intel_ds.h | 2 +- > arch/x86/include/asm/msr-index.h | 1 + > arch/x86/include/asm/perf_event.h | 50 ++- > arch/x86/include/uapi/asm/perf_regs.h | 23 +- > arch/x86/kernel/cpu/match.c | 31 ++ > arch/x86/kernel/perf_regs.c | 27 +- > 19 files changed, 1049 insertions(+), 119 deletions(-) > applied to osp1 oem-next, thanks
BugLink: https://bugs.launchpad.net/bugs/1848978 [Impact] There is no complete perf support for Comet Lake CPU. For Ice Lake, some changes has been included in v5.3, but still misses CPU IDs. [Fix] perf support for Comet Lake is based on previous works for Ice Lake, so changes for both have to be backported. [Test Case] On platforms with Comet Lake/Ice Lake CPUs, one should find new cstate_pkg events c{8,9,10}-residency appear in output of `perf list` for use. [Regression Potential] Low. This backports perf support for previously incompletedly supported cpu models. V2: - add one more patch from commit 6b89d4c1ae85 ("perf/x86/intel: Fix INTEL_FLAGS_EVENT_CONSTRAINT* masking"). Andi Kleen (3): perf/x86/kvm: Avoid unnecessary work in guest filtering perf/x86/intel: Extract memory code PEBS parser for reuse perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles them Kan Liang (14): x86/cpufeature: Add facility to check for min microcode revisions perf/x86: Support outputting XMM registers perf/x86/intel/ds: Extract code of event update in short period perf/x86/intel: Support adaptive PEBS v4 perf/x86/intel: Add Icelake support perf/x86/intel/uncore: Add Intel Icelake uncore support perf/x86/intel: Add Icelake desktop CPUID perf/x86/intel: Add more Icelake CPUIDs x86/cpu: Add Comet Lake to the Intel CPU models header perf/x86/intel: Add Comet Lake CPU support perf/x86/msr: Add Comet Lake CPU support perf/x86/cstate: Add Comet Lake CPU support perf/x86/msr: Add new CPU model numbers for Ice Lake perf/x86/cstate: Update C-state counters for Ice Lake Peter Zijlstra (1): perf/x86: Support constraint ranges Rajneesh Bhardwaj (1): perf/x86: Add Intel Ice Lake NNPI uncore support Stephane Eranian (1): perf/x86/intel: Fix INTEL_FLAGS_EVENT_CONSTRAINT* masking arch/x86/events/core.c | 15 + arch/x86/events/intel/core.c | 207 ++++++++++- arch/x86/events/intel/cstate.c | 41 ++- arch/x86/events/intel/ds.c | 505 ++++++++++++++++++++++---- arch/x86/events/intel/lbr.c | 35 +- arch/x86/events/intel/rapl.c | 1 + arch/x86/events/intel/uncore.c | 8 + arch/x86/events/intel/uncore.h | 1 + arch/x86/events/intel/uncore_snb.c | 91 +++++ arch/x86/events/msr.c | 5 + arch/x86/events/perf_event.h | 94 ++++- arch/x86/include/asm/cpu_device_id.h | 28 ++ arch/x86/include/asm/intel-family.h | 3 + arch/x86/include/asm/intel_ds.h | 2 +- arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/perf_event.h | 50 ++- arch/x86/include/uapi/asm/perf_regs.h | 23 +- arch/x86/kernel/cpu/match.c | 31 ++ arch/x86/kernel/perf_regs.c | 27 +- 19 files changed, 1049 insertions(+), 119 deletions(-)