| Message ID | ff2b2845-9520-4264-bc49-72075736d3b4@monstr.eu |
|---|---|
| State | Accepted |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | [GIT,PULL] xilinx patches for v2024.04-rc3 | expand |
On Wed, Feb 14, 2024 at 04:59:52PM +0100, Michal Simek wrote: > Hi Tom, > > please pull these patches to your branch. Most of them are related to device > tree and aligning with the latest dt schema for SR certification. > CI is not reporting any issue too. > > Thanks, > Michal > > > The following changes since commit e8f2404e093daf6cc3ac2b3233e3c6770d13e371: > > Merge branch 'master-779h0-r2' of > https://source.denx.de/u-boot/custodians/u-boot-sh (2024-02-11 12:42:25 > -0500) > > are available in the Git repository at: > > git@source.denx.de:u-boot/custodians/u-boot-microblaze.git > tags/xilinx-for-v2024.04-rc3 > > for you to fetch changes up to c2ad5fb616d4e8aa2ac00e224030589847731fbe: > > arm64: versal-net: Setup correct addresses of GICR/GICD (2024-02-14 > 11:23:43 +0100) > Applied to u-boot/master, thanks!
Hi Tom, please pull these patches to your branch. Most of them are related to device tree and aligning with the latest dt schema for SR certification. CI is not reporting any issue too. Thanks, Michal The following changes since commit e8f2404e093daf6cc3ac2b3233e3c6770d13e371: Merge branch 'master-779h0-r2' of https://source.denx.de/u-boot/custodians/u-boot-sh (2024-02-11 12:42:25 -0500) are available in the Git repository at: git@source.denx.de:u-boot/custodians/u-boot-microblaze.git tags/xilinx-for-v2024.04-rc3 for you to fetch changes up to c2ad5fb616d4e8aa2ac00e224030589847731fbe: arm64: versal-net: Setup correct addresses of GICR/GICD (2024-02-14 11:23:43 +0100) ---------------------------------------------------------------- Xilinx changes for v2024.04-rc3 zynqmp: - Cover missing _SE chip variants to fix fpga programming versal: - Enable LTO for mini configurations versal-net: - Enable LTO for mini configurations - Fix GIC address to aligned with real silicon xilinx: - DTs cleanup and fixups - Enable HTTP boot - Add missing spl header to zynqmp.c ---------------------------------------------------------------- Michal Simek (10): arm64: xilinx: Enable EFI_HTTP_BOOT by default arm64: zynqmp: Sync clock labels with kr260 revB arm64: zynqmp: Describe 25MHz fixed clock for PL GEMs arm64: zynqmp: Fix kr260 clock wiring xilinx: Fix fpga region DT nodes name arm64: zynqmp: Remove arm,cortex-a53-edac node arm64: zynqmp: Align nvmem-fw node with dt-schema arm64: zynqmp: Do not expose usbhub nodes on kr260 usb1 arm64: zynqmp: Disable DP on kd240 arm64: versal-net: Setup correct addresses of GICR/GICD Saeed Nowshadi (1): arm64: zynqmp: Add 'silabs, skip-recall' to all si570 clk nodes Venkatesh Yadav Abbarapu (4): soc: zynqmp: Add the IDcode for dr_SE and eg_SE variants configs: versal: Enable CONFIG_LTO for mini qspi/ospi configs: versal_net: Enable CONFIG_LTO for mini qspi/ospi xilinx: zynqmp: Add the missing function prototype arch/arm/dts/zynq-7000.dtsi | 2 +- arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 5 + arch/arm/dts/zynqmp-sck-kd-g-revA.dtso | 16 +++ arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 25 ++-- arch/arm/dts/zynqmp-sck-kr-g-revB.dtso | 8 ++ arch/arm/dts/zynqmp.dtsi | 131 ++++++++++---------- board/xilinx/zynqmp/zynqmp.c | 1 + configs/xilinx_versal_mini_ospi_defconfig | 1 + configs/xilinx_versal_mini_qspi_defconfig | 1 + configs/xilinx_versal_net_mini_ospi_defconfig | 1 + configs/xilinx_versal_net_mini_qspi_defconfig | 1 + configs/xilinx_versal_net_virt_defconfig | 1 + configs/xilinx_versal_virt_defconfig | 1 + configs/xilinx_zynqmp_kria_defconfig | 1 + configs/xilinx_zynqmp_virt_defconfig | 1 + drivers/soc/soc_xilinx_zynqmp.c | 28 ++++- include/configs/xilinx_versal_net.h | 4 +- 17 files changed, 149 insertions(+), 79 deletions(-)