| Message ID | fdf15bc579815452d6f59978938a0fbc90885764.1380539729.git.marcel@ziswiler.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Albert ARIBAUD |
| Headers | show |
Hi Marcel, On Mon, 30 Sep 2013 13:26:09 +0200, Marcel Ziswiler <marcel@ziswiler.com> wrote: > Add ANADIG PLL5 control definitions required for Ethernet RMII clock > configuration. > > Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> > --- > arch/arm/include/asm/arch-vf610/crm_regs.h | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h > index 04cc5bc..e17c7d1 100644 > --- a/arch/arm/include/asm/arch-vf610/crm_regs.h > +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h > @@ -187,6 +187,10 @@ struct anadig_reg { > #define CCM_CCGR9_FEC0_CTRL_MASK 0x3 > #define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) > > +#define ANADIG_PLL5_CTRL_BYPASS (1 << 16) > +#define ANADIG_PLL5_CTRL_ENABLE (1 << 13) > +#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12) > +#define ANADIG_PLL5_CTRL_DIV_SELECT 1 > #define ANADIG_PLL2_CTRL_ENABLE (1 << 13) > #define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) > #define ANADIG_PLL2_CTRL_DIV_SELECT 1 This and 3/10 could be merged as they touch the same file and do the same thing, adding definitions. Ditto for 06, 07 and 08/10 which all touch the same file. I'd even say all addition patches (3/10 to 8/10) could be grouped together in one logical change, like "add all definitions needed for vf610". Amicalement,
diff --git a/arch/arm/include/asm/arch-vf610/crm_regs.h b/arch/arm/include/asm/arch-vf610/crm_regs.h index 04cc5bc..e17c7d1 100644 --- a/arch/arm/include/asm/arch-vf610/crm_regs.h +++ b/arch/arm/include/asm/arch-vf610/crm_regs.h @@ -187,6 +187,10 @@ struct anadig_reg { #define CCM_CCGR9_FEC0_CTRL_MASK 0x3 #define CCM_CCGR9_FEC1_CTRL_MASK (0x3 << 2) +#define ANADIG_PLL5_CTRL_BYPASS (1 << 16) +#define ANADIG_PLL5_CTRL_ENABLE (1 << 13) +#define ANADIG_PLL5_CTRL_POWERDOWN (1 << 12) +#define ANADIG_PLL5_CTRL_DIV_SELECT 1 #define ANADIG_PLL2_CTRL_ENABLE (1 << 13) #define ANADIG_PLL2_CTRL_POWERDOWN (1 << 12) #define ANADIG_PLL2_CTRL_DIV_SELECT 1
Add ANADIG PLL5 control definitions required for Ethernet RMII clock configuration. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com> --- arch/arm/include/asm/arch-vf610/crm_regs.h | 4 ++++ 1 file changed, 4 insertions(+)