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[2/4] board: freescale: t208xrdb: add rev D support for the non-DM_ETH mode

Message ID c1cb4330cb24e8aaa93623eeb518f1f89618aef7.1623327658.git.camelia.groza@nxp.com
State Changes Requested
Delegated to: Tom Rini
Headers show
Series board: freescale: add T2080RDB rev D support | expand

Commit Message

Camelia Groza June 10, 2021, 12:39 p.m. UTC 
From: Camelia Groza <camelia.groza@nxp.com>

The T2080RDB boards revisions D and up have updated 10G Aquantia PHYs
connected to MAC1 and MAC2. The second Aquantia PHY is located at a
different address on the MDIO bus compared to rev C.

Account for these changes when initializing the board in the legacy
non-DM_ETH mode.

Signed-off-by: Camelia Groza <camelia.groza@nxp.com>
---
 board/freescale/t208xrdb/eth_t208xrdb.c | 16 ++++++++++++++--
 include/configs/T208xRDB.h              |  8 +++++---
 2 files changed, 19 insertions(+), 5 deletions(-)
diff mbox series

Patch

diff --git a/board/freescale/t208xrdb/eth_t208xrdb.c b/board/freescale/t208xrdb/eth_t208xrdb.c
index b0ff4b1f375a..d0329a87d281 100644
--- a/board/freescale/t208xrdb/eth_t208xrdb.c
+++ b/board/freescale/t208xrdb/eth_t208xrdb.c
@@ -26,6 +26,8 @@ 
 #include <fsl_dtsec.h>
 #include <asm/fsl_serdes.h>
 
+extern u8 get_hw_revision(void);
+
 int board_eth_init(struct bd_info *bis)
 {
 #if defined(CONFIG_FMAN_ENET)
@@ -34,6 +36,7 @@  int board_eth_init(struct bd_info *bis)
 	struct memac_mdio_info tgec_mdio_info;
 	struct mii_dev *dev;
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	int aq_phy_id_1, aq_phy_id_2;
 	u32 srds_s1;
 
 	srds_s1 = in_be32(&gur->rcwsr[4]) &
@@ -59,13 +62,22 @@  int board_eth_init(struct bd_info *bis)
 	fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
 	fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
 
+	/* The AQR PHY addresses differ between board revisions */
+	if (get_hw_revision() == 'C') {
+		aq_phy_id_1 = FM1_10GEC3_PHY_ADDR;
+		aq_phy_id_2 = FM1_10GEC4_PHY_ADDR;
+	} else {
+		aq_phy_id_1 = AQR113C_PHY_ADDR1;
+		aq_phy_id_2 = AQR113C_PHY_ADDR2;
+	}
+
 	switch (srds_s1) {
 	case 0x66:
 	case 0x6b:
 		fm_info_set_phy_address(FM1_10GEC1, CORTINA_PHY_ADDR1);
 		fm_info_set_phy_address(FM1_10GEC2, CORTINA_PHY_ADDR2);
-		fm_info_set_phy_address(FM1_10GEC3, FM1_10GEC3_PHY_ADDR);
-		fm_info_set_phy_address(FM1_10GEC4, FM1_10GEC4_PHY_ADDR);
+		fm_info_set_phy_address(FM1_10GEC3, aq_phy_id_1);
+		fm_info_set_phy_address(FM1_10GEC4, aq_phy_id_2);
 		break;
 	default:
 		printf("SerDes1 protocol 0x%x is not supported on T208xRDB\n",
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index e467ef453d2f..871f7db34501 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -1,7 +1,7 @@ 
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020 NXP
+ * Copyright 2020-2021 NXP
  */
 
 /*
@@ -537,8 +537,10 @@  unsigned long get_board_ddr_clk(void);
 #define RGMII_PHY2_ADDR		0x02
 #define CORTINA_PHY_ADDR1	0x0c  /* Cortina CS4315 */
 #define CORTINA_PHY_ADDR2	0x0d
-#define FM1_10GEC3_PHY_ADDR	0x00  /* Aquantia AQ1202 10G Base-T */
-#define FM1_10GEC4_PHY_ADDR	0x01
+#define FM1_10GEC3_PHY_ADDR	0x00  /* Aquantia AQ1202 10G Base-T used */
+#define FM1_10GEC4_PHY_ADDR	0x01  /* by board revision C */
+#define AQR113C_PHY_ADDR1	0x00  /* Aquantia AQR113C 10G Base-T used */
+#define AQR113C_PHY_ADDR2	0x08  /* by board revisions D and up. */
 #endif
 
 #ifdef CONFIG_FMAN_ENET