Message ID | be07aed81a6122f41d45a9f5a4390f1c194577e2.1624944246.git.Takahiro.Kuwano@infineon.com |
---|---|
State | Accepted |
Commit | c95a914aed7d8025b3877b04272aecf4e1b56ea4 |
Delegated to: | Jagannadha Sutradharudu Teki |
Headers | show |
Series | mtd: spi-nor: Add support for Cypress s25hl-t/s25hs-t | expand |
On Tue, Jun 29, 2021 at 11:31 AM <tkuw584924@gmail.com> wrote: > > From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> > > The S25HL-T/S25HS-T family is the Cypress Semper Flash with Quad SPI. > > https://www.cypress.com/file/424146/download (256Mb/512Mb/1Gb, single die) > https://www.cypress.com/file/499246/download (2Gb/4Gb, dual/quad die) > > The full version can be found in the following links (registration > required). > https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-Semper-Flash-with-Quad-SPI/ta-p/260789?attachment-id=19522 > https://community.cypress.com/t5/Semper-Flash-Access-Program/Datasheet-2Gb-MCP-Semper-Flash-with-Quad-SPI/ta-p/260823?attachment-id=29503 > > S25HL/HS-T (Semper Flash with Quad SPI) Family has user-configurable > sector architecture. By default, the 512Mb and 1Gb, single-die package > parts are configured to non-uniform that 4KB sectors overlaid on bottom > address. To support this, an erase hook makes overlaid sectors appear as > uniform sectors. The 2Gb, dual-die package parts are configured to uniform > by default. > > Tested on Xilinx Zynq-7000 FPGA board. > > Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> > Reviewed-by: Pratyush Yadav <p.yadav@ti.com> > --- Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 59f2d3e4d6..1af1c86486 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -225,6 +225,22 @@ const struct flash_info spi_nor_ids[] = { { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, { INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO6("s25hl512t", 0x342a1a, 0x0f0390, 256 * 1024, 256, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_CLSR) }, + { INFO6("s25hl01gt", 0x342a1b, 0x0f0390, 256 * 1024, 512, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_CLSR) }, + { INFO6("s25hl02gt", 0x342a1c, 0x0f0090, 256 * 1024, 1024, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO6("s25hs512t", 0x342b1a, 0x0f0390, 256 * 1024, 256, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_CLSR) }, + { INFO6("s25hs01gt", 0x342b1b, 0x0f0390, 256 * 1024, 512, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_CLSR) }, + { INFO6("s25hs02gt", 0x342b1c, 0x0f0090, 256 * 1024, 1024, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, #ifdef CONFIG_SPI_FLASH_S28HS512T { INFO("s28hs512t", 0x345b1a, 0, 256 * 1024, 256, SPI_NOR_OCTAL_DTR_READ) }, #endif