| Message ID | CAOMZO5Am3zXndQ8jwUR=0XDnZtkiGo8_DeRD937UMLU=8v2P+A@mail.gmail.com |
|---|---|
| State | Not Applicable |
| Delegated to: | Stefano Babic |
| Headers | show |
On 08.12.2014 16:36, Fabio Estevam wrote: >>>> Could you test this on one of your board? If your board also fails to >>>> boot >>>> via the "bmode mmc0" command if the CCGR0 register value is missing? >>> >>> >>> I am currently out of the office without access to my mx6 board, >> >> >> I see. Perhaps you could do that once you are back in the office... > > Sure, I will test it and will let you know how it goes. Thanks! > In the meantime, I am wondering if the change below would allow your > board to boot: > > --- a/arch/arm/cpu/armv7/mx6/soc.c > +++ b/arch/arm/cpu/armv7/mx6/soc.c > @@ -105,6 +105,10 @@ void init_aips(void) > #ifdef CONFIG_MX6SX > struct aipstz_regs *aips3; > #endif > + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; > + > + /* Turn on AIPS1 and AIPS2 clocks */ > + setbits_le32(&ccm->CCGR0, 0xf); > > aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; > aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR; I just tested it. And it doesn't help. I really think this code is not reached in this failure case. As the SPL is not loaded completely. Thanks, Stefan
Hi Stefan, On Mon, Dec 8, 2014 at 1:42 PM, Stefan Roese <sr@denx.de> wrote: > I just tested it. And it doesn't help. I really think this code is not > reached in this failure case. As the SPL is not loaded completely. Do you have this patch applied? commit f2863ff3f47c99c4b5ba00be572e3a2c4213c5a2 Author: Nikita Kiryanov <nikita@compulab.co.il> Date: Wed Oct 29 19:28:33 2014 +0200 arm: imx: make bmode command work with SPL/U-Boot combo The bmode command forces the SoC to use a specific boot device by writing its boot mode into SRC_GPR9, and notifying the SoC of the change using SRC_GPR10[28] bit: if the bit is on, bootROM uses the value in SRC_GPR9 instead of SRC_SMBR1 to determine the boot device. SPL on the other hand is oblivious to this distinction, so once the bootROM loads SPL from the device configured in SRC_GPR10, SPL will attempt to load U-Boot from the device configured in SRC_SMBR1, which is not updated by the bootROM to the value in SRC_GPR9. The result is that the selected boot device is not used across all the boot stages. Update spl_boot_device() to look at gpr9 when necessary. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Cc: Stefano Babic <sbabic@denx.de> Cc: Troy Kisky <troy.kisky@boundarydevices.com> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Heiko Schocher <hs@denx.de>
On 08.12.2014 17:13, Fabio Estevam wrote: >> I just tested it. And it doesn't help. I really think this code is not >> reached in this failure case. As the SPL is not loaded completely. > > Do you have this patch applied? > > commit f2863ff3f47c99c4b5ba00be572e3a2c4213c5a2 > Author: Nikita Kiryanov <nikita@compulab.co.il> > Date: Wed Oct 29 19:28:33 2014 +0200 > > arm: imx: make bmode command work with SPL/U-Boot combo > > The bmode command forces the SoC to use a specific boot device > by writing its boot mode into SRC_GPR9, and notifying the SoC of > the change using SRC_GPR10[28] bit: if the bit is on, bootROM > uses the value in SRC_GPR9 instead of SRC_SMBR1 to determine > the boot device. > > SPL on the other hand is oblivious to this distinction, so once > the bootROM loads SPL from the device configured in SRC_GPR10, > SPL will attempt to load U-Boot from the device configured in > SRC_SMBR1, which is not updated by the bootROM to the value in > SRC_GPR9. > > The result is that the selected boot device is not used across all > the boot stages. > > Update spl_boot_device() to look at gpr9 when necessary. > > Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> > Cc: Stefano Babic <sbabic@denx.de> > Cc: Troy Kisky <troy.kisky@boundarydevices.com> > Cc: Tim Harvey <tharvey@gateworks.com> > Cc: Eric Nelson <eric.nelson@boundarydevices.com> > Cc: Fabio Estevam <fabio.estevam@freescale.com> > Cc: Heiko Schocher <hs@denx.de> Yes, its applied. I'm nearly on mainline right now. And it doesn't help. Which makes sense if my current guess is correct, that the BootROM doesn't load the SPL completely without this CCGR0 register setting in the DCD. Thanks, Stefan
Hi Stefan, On Mon, Dec 8, 2014 at 2:27 PM, Stefan Roese <sr@denx.de> wrote: > Yes, its applied. I'm nearly on mainline right now. And it doesn't help. > Which makes sense if my current guess is correct, that the BootROM doesn't > load the SPL completely without this CCGR0 register setting in the DCD. On a mx6qsabresd booting via SPL: U-Boot SPL 2015.01-rc3-00158-ge3bf81b (Dec 18 2014 - 11:19:37) U-Boot 2015.01-rc3-00158-ge3bf81b (Dec 18 2014 - 11:19:37) CPU: Freescale i.MX6Q rev1.2 at 792 MHz CPU: Temperature 46 C Reset cause: POR Board: MX6-SabreSD I2C: ready DRAM: 1 GiB PMIC: PFUZE100 ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 *** Warning - bad CRC, using default environment No panel detected: default to Hannstar-XGA Display: Hannstar-XGA (1024x768) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 => bmode sd3 resetting ... U-Boot SPL 2015.01-rc3-00158-ge3bf81b (Dec 18 2014 - 11:19:37) U-Boot 2015.01-rc3-00158-ge3bf81b (Dec 18 2014 - 11:19:37) CPU: Freescale i.MX6Q rev1.2 at 792 MHz CPU: Temperature 47 C Reset cause: WDOG Board: MX6-SabreSD I2C: ready DRAM: 1 GiB PMIC: PFUZE100 ID=0x10 MMC: FSL_SDHC: 0, FSL_SDHC: 1, FSL_SDHC: 2 *** Warning - bad CRC, using default environment No panel detected: default to Hannstar-XGA Display: Hannstar-XGA (1024x768) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 => However if I move the SD card into SD2 slot, then it fails: => bmode sd2 resetting ... U-Boot SPL 2015.01-rc3-00158-ge3bf81b (Dec 18 2014 - 11:19:37) MMC: no card present spl: mmc init failed: err - -16 ### ERROR ### Please RESET the board ### The spl loaded, but it failed to load U-boot. Probably because SPL did not initialized SD2, so it seems things are working fine here.
--- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -105,6 +105,10 @@ void init_aips(void) #ifdef CONFIG_MX6SX struct aipstz_regs *aips3; #endif + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* Turn on AIPS1 and AIPS2 clocks */ + setbits_le32(&ccm->CCGR0, 0xf); aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR; aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;