Message ID | BLU436-SMTP22DD3FF958DC8AAA09BDA0FF4D0@phx.gbl |
---|---|
State | Superseded |
Delegated to: | Daniel Schwierzeck |
Headers | show |
On 05/22/2016 05:59 AM, Wills Wang wrote: > Use function "pll_init" for ath79 platform PLL initialization, > and put it into mach/clk.h > > Signed-off-by: Wills Wang <wills.wang@live.com> > --- > > arch/mips/mach-ath79/ar934x/clk.c | 2 +- > arch/mips/mach-ath79/include/mach/ath79.h | 2 -- > arch/mips/mach-ath79/include/mach/clk.h | 12 ++++++++++++ > board/tplink/wdr4300/wdr4300.c | 6 +++--- > 4 files changed, 16 insertions(+), 6 deletions(-) > create mode 100644 arch/mips/mach-ath79/include/mach/clk.h > > diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c > index fdbbc80..97d0e09 100644 > --- a/arch/mips/mach-ath79/ar934x/clk.c > +++ b/arch/mips/mach-ath79/ar934x/clk.c > @@ -101,7 +101,7 @@ static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) > } while (reg >= 0x40000); > } > > -void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz) > +void pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz) Same comment I had in 5/7 applies here > { > void __iomem *srif_regs = map_physmem(AR934X_SRIF_BASE, > AR934X_SRIF_SIZE, MAP_NOCACHE); > diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h > index fdc1149..90d80b8 100644 > --- a/arch/mips/mach-ath79/include/mach/ath79.h > +++ b/arch/mips/mach-ath79/include/mach/ath79.h > @@ -140,6 +140,4 @@ static inline int soc_is_qca956x(void) > return soc_is_tp9343() || soc_is_qca9561(); > } > > -void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz); > - > #endif /* __ASM_MACH_ATH79_H */ > diff --git a/arch/mips/mach-ath79/include/mach/clk.h b/arch/mips/mach-ath79/include/mach/clk.h > new file mode 100644 > index 0000000..58be7ea > --- /dev/null > +++ b/arch/mips/mach-ath79/include/mach/clk.h > @@ -0,0 +1,12 @@ > +/* > + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __ASM_MACH_CLK_H > +#define __ASM_MACH_CLK_H > + > +void pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 bus_mhz); Same comment I had in 3/7 applies here. > + > +#endif /* __ASM_MACH_CLK_H */ > diff --git a/board/tplink/wdr4300/wdr4300.c b/board/tplink/wdr4300/wdr4300.c > index bff3938..b6c2881 100644 > --- a/board/tplink/wdr4300/wdr4300.c > +++ b/board/tplink/wdr4300/wdr4300.c > @@ -8,10 +8,10 @@ > #include <asm/io.h> > #include <asm/addrspace.h> > #include <asm/types.h> > -#include <mach/ath79.h> > -#include <mach/reset.h> > #include <mach/ar71xx_regs.h> > #include <mach/ddr.h> > +#include <mach/clk.h> > +#include <mach/reset.h> > #include <debug_uart.h> > > DECLARE_GLOBAL_DATA_PTR; > @@ -63,7 +63,7 @@ int board_early_init_f(void) > #endif > > #ifndef CONFIG_SKIP_LOWLEVEL_INIT > - ar934x_pll_init(560, 480, 240); > + pll_init(560, 480, 240); > ddr_init(560, 480, 240); > #endif > >
diff --git a/arch/mips/mach-ath79/ar934x/clk.c b/arch/mips/mach-ath79/ar934x/clk.c index fdbbc80..97d0e09 100644 --- a/arch/mips/mach-ath79/ar934x/clk.c +++ b/arch/mips/mach-ath79/ar934x/clk.c @@ -101,7 +101,7 @@ static void ar934x_srif_pll_cfg(void __iomem *pll_reg_base, const u32 srif_val) } while (reg >= 0x40000); } -void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz) +void pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz) { void __iomem *srif_regs = map_physmem(AR934X_SRIF_BASE, AR934X_SRIF_SIZE, MAP_NOCACHE); diff --git a/arch/mips/mach-ath79/include/mach/ath79.h b/arch/mips/mach-ath79/include/mach/ath79.h index fdc1149..90d80b8 100644 --- a/arch/mips/mach-ath79/include/mach/ath79.h +++ b/arch/mips/mach-ath79/include/mach/ath79.h @@ -140,6 +140,4 @@ static inline int soc_is_qca956x(void) return soc_is_tp9343() || soc_is_qca9561(); } -void ar934x_pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 ahb_mhz); - #endif /* __ASM_MACH_ATH79_H */ diff --git a/arch/mips/mach-ath79/include/mach/clk.h b/arch/mips/mach-ath79/include/mach/clk.h new file mode 100644 index 0000000..58be7ea --- /dev/null +++ b/arch/mips/mach-ath79/include/mach/clk.h @@ -0,0 +1,12 @@ +/* + * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_MACH_CLK_H +#define __ASM_MACH_CLK_H + +void pll_init(const u16 cpu_mhz, const u16 ddr_mhz, const u16 bus_mhz); + +#endif /* __ASM_MACH_CLK_H */ diff --git a/board/tplink/wdr4300/wdr4300.c b/board/tplink/wdr4300/wdr4300.c index bff3938..b6c2881 100644 --- a/board/tplink/wdr4300/wdr4300.c +++ b/board/tplink/wdr4300/wdr4300.c @@ -8,10 +8,10 @@ #include <asm/io.h> #include <asm/addrspace.h> #include <asm/types.h> -#include <mach/ath79.h> -#include <mach/reset.h> #include <mach/ar71xx_regs.h> #include <mach/ddr.h> +#include <mach/clk.h> +#include <mach/reset.h> #include <debug_uart.h> DECLARE_GLOBAL_DATA_PTR; @@ -63,7 +63,7 @@ int board_early_init_f(void) #endif #ifndef CONFIG_SKIP_LOWLEVEL_INIT - ar934x_pll_init(560, 480, 240); + pll_init(560, 480, 240); ddr_init(560, 480, 240); #endif
Use function "pll_init" for ath79 platform PLL initialization, and put it into mach/clk.h Signed-off-by: Wills Wang <wills.wang@live.com> --- arch/mips/mach-ath79/ar934x/clk.c | 2 +- arch/mips/mach-ath79/include/mach/ath79.h | 2 -- arch/mips/mach-ath79/include/mach/clk.h | 12 ++++++++++++ board/tplink/wdr4300/wdr4300.c | 6 +++--- 4 files changed, 16 insertions(+), 6 deletions(-) create mode 100644 arch/mips/mach-ath79/include/mach/clk.h