diff mbox series

riscv: Extend board compatible string with "qemu,mbv"

Message ID 575ac34167776f3a3a00aa23cc5e182d1e41492f.1703084004.git.michal.simek@amd.com
State Accepted
Commit 670db88c79ce88ff6c053f6507404bd6752b664f
Delegated to: Andes
Headers show
Series riscv: Extend board compatible string with "qemu,mbv" | expand

Commit Message

Michal Simek Dec. 20, 2023, 2:53 p.m. UTC 
Extend compatible string to match the latest change in dt binding.

Fixes: 7576ab2facae ("riscv: Add support for AMD/Xilinx MicroBlaze V")
Signed-off-by: Michal Simek <michal.simek@amd.com>
---

dt binding patch is available here.
https://lore.kernel.org/all/69670e5a46c98a2eb73d4f2e2d571a27c46b4640.1700722941.git.michal.simek@amd.com/

---
 arch/riscv/dts/xilinx-mbv32.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Leo Liang Dec. 21, 2023, 10:05 a.m. UTC | #1 
On Wed, Dec 20, 2023 at 03:53:28PM +0100, Michal Simek wrote:
> Extend compatible string to match the latest change in dt binding.
> 
> Fixes: 7576ab2facae ("riscv: Add support for AMD/Xilinx MicroBlaze V")
> Signed-off-by: Michal Simek <michal.simek@amd.com>
> ---
> 
> dt binding patch is available here.
> https://lore.kernel.org/all/69670e5a46c98a2eb73d4f2e2d571a27c46b4640.1700722941.git.michal.simek@amd.com/
> 
> ---
>  arch/riscv/dts/xilinx-mbv32.dts | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
diff mbox series

Patch

diff --git a/arch/riscv/dts/xilinx-mbv32.dts b/arch/riscv/dts/xilinx-mbv32.dts
index 6a6b8b694bd1..94e42c268115 100644
--- a/arch/riscv/dts/xilinx-mbv32.dts
+++ b/arch/riscv/dts/xilinx-mbv32.dts
@@ -12,7 +12,7 @@ 
 	#address-cells = <1>;
 	#size-cells = <1>;
 	model = "AMD MicroBlaze V 32bit";
-	compatible = "amd,mbv";
+	compatible = "qemu,mbv", "amd,mbv";
 
 	cpus: cpus {
 		#address-cells = <1>;