diff mbox series

[v2,11/32] arm: dts: mt7622: force high-speed mode for uart

Message ID 485c39decebd661a15e9fcd19e64557fcf000ef6.1661941661.git.weijie.gao@mediatek.com
State Superseded
Delegated to: Tom Rini
Headers show
Series Add support for MediaTek MT7981/MT7986 SoCs - v2 | expand

Commit Message

Weijie Gao (高惟杰) Aug. 31, 2022, 11:04 a.m. UTC 
The input clock for uart is too slow (25MHz) which introduces frequent data
error on both receiving and transmitting even if the baudrate is 115200.

Using high-speed can significantly solve this issue.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
---
v2 changes: none
---
 arch/arm/dts/mt7622.dtsi | 1 +
 1 file changed, 1 insertion(+)

Comments

Daniel Golle Sept. 1, 2022, 12:23 a.m. UTC | #1 
On Wed, Aug 31, 2022 at 07:04:34PM +0800, Weijie Gao wrote:
> The input clock for uart is too slow (25MHz) which introduces frequent data
> error on both receiving and transmitting even if the baudrate is 115200.
> 
> Using high-speed can significantly solve this issue.

Tested on Bananapi BPi-R64 (MT7622).
Fixes unstable console issues previously observed on MT7622 systems.

Tested-by: Daniel Golle <daniel@makrotopia.org>

> 
> Reviewed-by: Simon Glass <sjg@chromium.org>
> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
> ---
> v2 changes: none
> ---
>  arch/arm/dts/mt7622.dtsi | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
> index 0127474c95..fb6c1b7154 100644
> --- a/arch/arm/dts/mt7622.dtsi
> +++ b/arch/arm/dts/mt7622.dtsi
> @@ -175,6 +175,7 @@
>  		status = "disabled";
>  		assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
>  		assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
> +		mediatek,force-highspeed;
>  	};
>  
>  	mmc0: mmc@11230000 {
> -- 
> 2.17.1
>
diff mbox series

Patch

diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
index 0127474c95..fb6c1b7154 100644
--- a/arch/arm/dts/mt7622.dtsi
+++ b/arch/arm/dts/mt7622.dtsi
@@ -175,6 +175,7 @@ 
 		status = "disabled";
 		assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
 		assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
+		mediatek,force-highspeed;
 	};
 
 	mmc0: mmc@11230000 {