| Message ID | 332b2106d7a8190dd1001b5387f8bd1fba2e061b.1648205405.git.michal.simek@xilinx.com |
|---|---|
| State | Accepted |
| Commit | cbeba3515208c9e8db3dba3d5af5ec838c1065b3 |
| Delegated to: | Michal Simek |
| Headers | show |
| Series | serial: zynq: Change fifor behavior in debug mode | expand |
pá 25. 3. 2022 v 11:50 odesílatel Michal Simek <michal.simek@xilinx.com> napsal: > > Serial IP has output buffer which status is indicated by two bits. If fifo > if empty or full. Default configuration is that chars are pushed to fifo > till it is full. Time to time it is visible that chars are scambled and > logs are not visible. Not sure what it is exactly happening but all the > time it helps to change driver behavior to write only one char at a time. > That's why enable this mode when debug uart is enabled not to see scrambled > chars in debug by default. > > Signed-off-by: Michal Simek <michal.simek@xilinx.com> > --- > > drivers/serial/serial_zynq.c | 10 ++++++++-- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c > index fd999368ab70..6bb003dc1558 100644 > --- a/drivers/serial/serial_zynq.c > +++ b/drivers/serial/serial_zynq.c > @@ -21,6 +21,7 @@ > > #define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */ > #define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */ > +#define ZYNQ_UART_SR_TXEMPTY BIT(3) /* TX FIFO empty */ > #define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */ > > #define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */ > @@ -107,8 +108,13 @@ static void _uart_zynq_serial_init(struct uart_zynq *regs) > > static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) > { > - if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) > - return -EAGAIN; > + if (CONFIG_IS_ENABLED(DEBUG_UART_ZYNQ)) { > + if (!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXEMPTY)) > + return -EAGAIN; > + } else { > + if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) > + return -EAGAIN; > + } > > writel(c, ®s->tx_rx_fifo); > > -- > 2.35.1 > Applied with subject s/fifor/fifo/ fixed M
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index fd999368ab70..6bb003dc1558 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -21,6 +21,7 @@ #define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */ #define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */ +#define ZYNQ_UART_SR_TXEMPTY BIT(3) /* TX FIFO empty */ #define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */ #define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */ @@ -107,8 +108,13 @@ static void _uart_zynq_serial_init(struct uart_zynq *regs) static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) { - if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) - return -EAGAIN; + if (CONFIG_IS_ENABLED(DEBUG_UART_ZYNQ)) { + if (!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXEMPTY)) + return -EAGAIN; + } else { + if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) + return -EAGAIN; + } writel(c, ®s->tx_rx_fifo);
Serial IP has output buffer which status is indicated by two bits. If fifo if empty or full. Default configuration is that chars are pushed to fifo till it is full. Time to time it is visible that chars are scambled and logs are not visible. Not sure what it is exactly happening but all the time it helps to change driver behavior to write only one char at a time. That's why enable this mode when debug uart is enabled not to see scrambled chars in debug by default. Signed-off-by: Michal Simek <michal.simek@xilinx.com> --- drivers/serial/serial_zynq.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-)