| Message ID | 20240502-msm8916-hs-usb-clocks-v1-1-eeccf483b68d@samcday.com |
|---|---|
| State | Superseded |
| Delegated to: | Caleb Connolly |
| Headers | show |
| Series | qcom: ehci: enable core + iface clocks | expand |
On 02/05/2024 15:16, Sam Day wrote: > The newer "register map for simple gate clocks" support added for qcom > clocks is used. As a result gcc_apq8016 now has a mixture of the old and > new styles. I didn't (and still don't!) feel comfortable enough in this > area to update the existing code. > > Some groundwork was also laid to dump the state of these gate clocks > with the recently-added qcom dump callbacks. I'm not sure which part of the patch you're referring to, but the dump callbacks aren't in upstream yet. > > Signed-off-by: Sam Day <me@samcday.com> > --- > drivers/clk/qcom/clock-apq8016.c | 31 +++++++++++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > > diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c > index d3b63b9c1a..745371a289 100644 > --- a/drivers/clk/qcom/clock-apq8016.c > +++ b/drivers/clk/qcom/clock-apq8016.c > @@ -17,6 +17,8 @@ > > #include "clock-qcom.h" > > +#define USB_HS_SYSTEM_CLK_CMD_RCGR 0x41010 > + > /* Clocks: (from CLK_CTL_BASE) */ > #define GPLL0_STATUS (0x2101C) > #define APCS_GPLL_ENA_VOTE (0x45000) > @@ -39,6 +41,11 @@ > /* GPLL0 clock control registers */ > #define GPLL0_STATUS_ACTIVE BIT(17) > > +static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { > + F(80000000, CFG_CLK_SRC_GPLL0, 10, 0, 0), Since this is just one entry, it probably makes more sense to just put the literal values in the clk_rcg_set_rate_mnd(). This makes it clear that there's only one actual frequency, and we have the kernel for reference anyway. > + { } > +}; > + > static struct pll_vote_clk gpll0_vote_clk = { > .status = GPLL0_STATUS, > .status_bit = GPLL0_STATUS_ACTIVE, > @@ -52,6 +59,11 @@ static struct vote_clk gcc_blsp1_ahb_clk = { > .vote_bit = BIT(10), > }; > > +static const struct gate_clk apq8016_clks[] = { Please define the size of this array, or add a bounds check in apq8016_clk_enable() (I know this is missing for some of the other drivers). > + GATE_CLK(GCC_USB_HS_AHB_CLK, 0x41008, 0x00000001), > + GATE_CLK(GCC_USB_HS_SYSTEM_CLK, 0x41004, 0x00000001), > +}; > + > /* SDHCI */ > static int apq8016_clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) > { > @@ -106,6 +118,7 @@ int apq8016_clk_init_uart(phys_addr_t base, unsigned long id) > > static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate) > { > + const struct freq_tbl *freq; > struct msm_clk_priv *priv = dev_get_priv(clk->dev); > > switch (clk->id) { > @@ -117,13 +130,31 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate) > case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */ > apq8016_clk_init_uart(priv->base, clk->id); > return 7372800; > + case GCC_USB_HS_SYSTEM_CLK: > + freq = qcom_find_freq(ftbl_gcc_usb_hs_system_clk, rate); As there is only one valid "rate" for this clock, I would be in favour of a log_warn() if the rate is wrong (it should be 80000000). Thanks and regards, > + clk_rcg_set_rate_mnd(priv->base, USB_HS_SYSTEM_CLK_CMD_RCGR, > + freq->pre_div, freq->m, freq->n, freq->src, 0); > + return freq->freq; > default: > return 0; > } > } > > +static int apq8016_clk_enable(struct clk *clk) > +{ > + struct msm_clk_priv *priv = dev_get_priv(clk->dev); > + > + debug("%s: clk %s\n", __func__, apq8016_clks[clk->id].name); > + qcom_gate_clk_en(priv, clk->id); > + > + return 0; > +} > + > static struct msm_clk_data apq8016_clk_data = { > .set_rate = apq8016_clk_set_rate, > + .clks = apq8016_clks, > + .num_clks = ARRAY_SIZE(apq8016_clks), > + .enable = apq8016_clk_enable, > }; > > static const struct udevice_id gcc_apq8016_of_match[] = { >
diff --git a/drivers/clk/qcom/clock-apq8016.c b/drivers/clk/qcom/clock-apq8016.c index d3b63b9c1a..745371a289 100644 --- a/drivers/clk/qcom/clock-apq8016.c +++ b/drivers/clk/qcom/clock-apq8016.c @@ -17,6 +17,8 @@ #include "clock-qcom.h" +#define USB_HS_SYSTEM_CLK_CMD_RCGR 0x41010 + /* Clocks: (from CLK_CTL_BASE) */ #define GPLL0_STATUS (0x2101C) #define APCS_GPLL_ENA_VOTE (0x45000) @@ -39,6 +41,11 @@ /* GPLL0 clock control registers */ #define GPLL0_STATUS_ACTIVE BIT(17) +static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = { + F(80000000, CFG_CLK_SRC_GPLL0, 10, 0, 0), + { } +}; + static struct pll_vote_clk gpll0_vote_clk = { .status = GPLL0_STATUS, .status_bit = GPLL0_STATUS_ACTIVE, @@ -52,6 +59,11 @@ static struct vote_clk gcc_blsp1_ahb_clk = { .vote_bit = BIT(10), }; +static const struct gate_clk apq8016_clks[] = { + GATE_CLK(GCC_USB_HS_AHB_CLK, 0x41008, 0x00000001), + GATE_CLK(GCC_USB_HS_SYSTEM_CLK, 0x41004, 0x00000001), +}; + /* SDHCI */ static int apq8016_clk_init_sdc(struct msm_clk_priv *priv, int slot, uint rate) { @@ -106,6 +118,7 @@ int apq8016_clk_init_uart(phys_addr_t base, unsigned long id) static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate) { + const struct freq_tbl *freq; struct msm_clk_priv *priv = dev_get_priv(clk->dev); switch (clk->id) { @@ -117,13 +130,31 @@ static ulong apq8016_clk_set_rate(struct clk *clk, ulong rate) case GCC_BLSP1_UART2_APPS_CLK: /* UART2 */ apq8016_clk_init_uart(priv->base, clk->id); return 7372800; + case GCC_USB_HS_SYSTEM_CLK: + freq = qcom_find_freq(ftbl_gcc_usb_hs_system_clk, rate); + clk_rcg_set_rate_mnd(priv->base, USB_HS_SYSTEM_CLK_CMD_RCGR, + freq->pre_div, freq->m, freq->n, freq->src, 0); + return freq->freq; default: return 0; } } +static int apq8016_clk_enable(struct clk *clk) +{ + struct msm_clk_priv *priv = dev_get_priv(clk->dev); + + debug("%s: clk %s\n", __func__, apq8016_clks[clk->id].name); + qcom_gate_clk_en(priv, clk->id); + + return 0; +} + static struct msm_clk_data apq8016_clk_data = { .set_rate = apq8016_clk_set_rate, + .clks = apq8016_clks, + .num_clks = ARRAY_SIZE(apq8016_clks), + .enable = apq8016_clk_enable, }; static const struct udevice_id gcc_apq8016_of_match[] = {
The newer "register map for simple gate clocks" support added for qcom clocks is used. As a result gcc_apq8016 now has a mixture of the old and new styles. I didn't (and still don't!) feel comfortable enough in this area to update the existing code. Some groundwork was also laid to dump the state of these gate clocks with the recently-added qcom dump callbacks. Signed-off-by: Sam Day <me@samcday.com> --- drivers/clk/qcom/clock-apq8016.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+)