| Message ID | 20240413134352.46495-1-dazen@189.cn |
|---|---|
| State | Changes Requested |
| Delegated to: | Andre Przywara |
| Headers | show |
| Series | DRAM_SUN50I_H616_TRIM_SIZE | expand |
On Sat, 13 Apr 2024 21:43:52 +0800 dazen@189.cn wrote: Hi, thanks for sending a patch! > From: lalakii <dazen@189.cn> > > Add "DRAM_SUN50I_H616_TRIM_SIZE" option for 1.5gb board. > > Signed-off-by: lalakii <dazen@189.cn> > --- > arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h | 1 + > arch/arm/mach-sunxi/Kconfig | 7 +++++++ > arch/arm/mach-sunxi/dram_sun50i_h616.c | 11 ++++++++++- > 3 files changed, 18 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h > index a8fdda124a..2d2526fead 100644 > --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h > +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h > @@ -166,6 +166,7 @@ struct dram_config { > u8 rows; > u8 ranks; > u8 bus_full_width; > + bool trim_size; > }; > > static inline int ns_to_t(int nanoseconds) > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig > index fe89aec6b9..255a498557 100644 > --- a/arch/arm/mach-sunxi/Kconfig > +++ b/arch/arm/mach-sunxi/Kconfig > @@ -108,6 +108,13 @@ config DRAM_SUN50I_H616_TPR12 > default 0x0 > help > TPR12 value from vendor DRAM settings. > + > +config DRAM_SUN50I_H616_TRIM_SIZE > + bool "H616 DRAM trim size" > + help > + Due to unknown issue, some H616 based boards may need to trim Well, it's not really an unknown issue, is it? The problem seems to be that the auto detection code cannot deal with the topology of the 1.5GB DRAM chips. The general problem with this approach is that it would need to be enabled at build time, which means the generated image will always trim the DRAM size, and would not be universal for each board anymore. So we need something to auto-detect this situation. Can you describe the failure mode, without this patch? Does the DRAM init code hang or give up already, or does this all pass, and then later on the board hangs or crashes when we try access the missing DRAM area? Maybe a small test access beyond 1.5GB would be able to check for this particular case? Cheers, Andre > + size a bit. > + > endif > > config SUN6I_PRCM > diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c > index 37c139e0ee..4598d60a57 100644 > --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c > +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c > @@ -1349,8 +1349,15 @@ static unsigned long mctl_calc_size(const struct dram_config *config) > { > u8 width = config->bus_full_width ? 4 : 2; > > + unsigned long size; > + > + size = (1ULL << (config->cols + config->rows + 3)) * width * config->ranks; > + > + if (config->trim_size) > + size = (size * 3) / (width == 4 ? 4 : 8); > + > /* 8 banks */ > - return (1ULL << (config->cols + config->rows + 3)) * width * config->ranks; > + return size; > } > > static const struct dram_para para = { > @@ -1379,6 +1386,8 @@ unsigned long sunxi_dram_init(void) > struct sunxi_prcm_reg *const prcm = > (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; > struct dram_config config; > + if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_TRIM_SIZE)) > + config.trim_size = true; > unsigned long size; > > setbits_le32(&prcm->res_cal_ctrl, BIT(8));
Dne ponedeljek, 15. april 2024 ob 02:22:45 GMT +2 je Andre Przywara napisal(a): > On Sat, 13 Apr 2024 21:43:52 +0800 > dazen@189.cn wrote: > > Hi, > > thanks for sending a patch! > > > From: lalakii <dazen@189.cn> > > > > Add "DRAM_SUN50I_H616_TRIM_SIZE" option for 1.5gb board. > > > > Signed-off-by: lalakii <dazen@189.cn> > > --- > > arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h | 1 + > > arch/arm/mach-sunxi/Kconfig | 7 +++++++ > > arch/arm/mach-sunxi/dram_sun50i_h616.c | 11 ++++++++++- > > 3 files changed, 18 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h > > index a8fdda124a..2d2526fead 100644 > > --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h > > +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h > > @@ -166,6 +166,7 @@ struct dram_config { > > u8 rows; > > u8 ranks; > > u8 bus_full_width; > > + bool trim_size; > > }; > > > > static inline int ns_to_t(int nanoseconds) > > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig > > index fe89aec6b9..255a498557 100644 > > --- a/arch/arm/mach-sunxi/Kconfig > > +++ b/arch/arm/mach-sunxi/Kconfig > > @@ -108,6 +108,13 @@ config DRAM_SUN50I_H616_TPR12 > > default 0x0 > > help > > TPR12 value from vendor DRAM settings. > > + > > +config DRAM_SUN50I_H616_TRIM_SIZE > > + bool "H616 DRAM trim size" > > + help > > + Due to unknown issue, some H616 based boards may need to trim > > Well, it's not really an unknown issue, is it? The problem seems to be > that the auto detection code cannot deal with the topology of the 1.5GB > DRAM chips. > > The general problem with this approach is that it would need to be > enabled at build time, which means the generated image will always trim > the DRAM size, and would not be universal for each board anymore. > > So we need something to auto-detect this situation. Can you describe > the failure mode, without this patch? Does the DRAM init code hang or > give up already, or does this all pass, and then later on the board > hangs or crashes when we try access the missing DRAM area? > Maybe a small test access beyond 1.5GB would be able to check for this > particular case? Vendor DRAM check for 1.5 GB is pretty simple. First, it's checked if 2 GB of RAM is detected. If so, 3 different patterns are written to 0x70000000, 0xa0000000 and 0x80000000 (in that order). Then, pattern from 0xa0000000 is read. If it doesn't match to pattern written to this location, 1.5 GB is assumed. Best regards, Jernej > > Cheers, > Andre > > > > + size a bit. > > + > > endif > > > > config SUN6I_PRCM > > diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c > > index 37c139e0ee..4598d60a57 100644 > > --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c > > +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c > > @@ -1349,8 +1349,15 @@ static unsigned long mctl_calc_size(const struct dram_config *config) > > { > > u8 width = config->bus_full_width ? 4 : 2; > > > > + unsigned long size; > > + > > + size = (1ULL << (config->cols + config->rows + 3)) * width * config->ranks; > > + > > + if (config->trim_size) > > + size = (size * 3) / (width == 4 ? 4 : 8); > > + > > /* 8 banks */ > > - return (1ULL << (config->cols + config->rows + 3)) * width * config->ranks; > > + return size; > > } > > > > static const struct dram_para para = { > > @@ -1379,6 +1386,8 @@ unsigned long sunxi_dram_init(void) > > struct sunxi_prcm_reg *const prcm = > > (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; > > struct dram_config config; > > + if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_TRIM_SIZE)) > > + config.trim_size = true; > > unsigned long size; > > > > setbits_le32(&prcm->res_cal_ctrl, BIT(8)); > >
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h index a8fdda124a..2d2526fead 100644 --- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h +++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h @@ -166,6 +166,7 @@ struct dram_config { u8 rows; u8 ranks; u8 bus_full_width; + bool trim_size; }; static inline int ns_to_t(int nanoseconds) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index fe89aec6b9..255a498557 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -108,6 +108,13 @@ config DRAM_SUN50I_H616_TPR12 default 0x0 help TPR12 value from vendor DRAM settings. + +config DRAM_SUN50I_H616_TRIM_SIZE + bool "H616 DRAM trim size" + help + Due to unknown issue, some H616 based boards may need to trim + size a bit. + endif config SUN6I_PRCM diff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c index 37c139e0ee..4598d60a57 100644 --- a/arch/arm/mach-sunxi/dram_sun50i_h616.c +++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c @@ -1349,8 +1349,15 @@ static unsigned long mctl_calc_size(const struct dram_config *config) { u8 width = config->bus_full_width ? 4 : 2; + unsigned long size; + + size = (1ULL << (config->cols + config->rows + 3)) * width * config->ranks; + + if (config->trim_size) + size = (size * 3) / (width == 4 ? 4 : 8); + /* 8 banks */ - return (1ULL << (config->cols + config->rows + 3)) * width * config->ranks; + return size; } static const struct dram_para para = { @@ -1379,6 +1386,8 @@ unsigned long sunxi_dram_init(void) struct sunxi_prcm_reg *const prcm = (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE; struct dram_config config; + if (IS_ENABLED(CONFIG_DRAM_SUN50I_H616_TRIM_SIZE)) + config.trim_size = true; unsigned long size; setbits_le32(&prcm->res_cal_ctrl, BIT(8));