diff mbox series

[03/11] spi: cadence-quadspi: Enable DDR bit for DTR commands

Message ID 20240411223709.573-4-greg.malysa@timesys.com
State New
Delegated to: Jagannadha Sutradharudu Teki
Headers show
Series cadence-qspi: Add DTR support including PHY mode calibration | expand

Commit Message

Greg Malysa April 11, 2024, 10:36 p.m. UTC 
From: Ian Roberts <ian.roberts@timesys.com>

The Cadence octal SPI IP read instruction register requires a bit to be
set to indicate if the read opcode is a compliant DDR read command.

Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com>
Signed-off-by: Greg Malysa <greg.malysa@timesys.com>
Signed-off-by: Ian Roberts <ian.roberts@timesys.com>
---

 drivers/spi/cadence_qspi.h     | 1 +
 drivers/spi/cadence_qspi_apb.c | 4 ++++
 2 files changed, 5 insertions(+)
diff mbox series

Patch

diff --git a/drivers/spi/cadence_qspi.h b/drivers/spi/cadence_qspi.h
index 693474a287..72e92cc997 100644
--- a/drivers/spi/cadence_qspi.h
+++ b/drivers/spi/cadence_qspi.h
@@ -61,6 +61,7 @@ 
 #define CQSPI_REG_RD_INSTR                      0x04
 #define CQSPI_REG_RD_INSTR_OPCODE_LSB           0
 #define CQSPI_REG_RD_INSTR_TYPE_INSTR_LSB       8
+#define CQSPI_REG_RD_INSTR_DDR_EN_MASK          BIT(10)
 #define CQSPI_REG_RD_INSTR_TYPE_ADDR_LSB        12
 #define CQSPI_REG_RD_INSTR_TYPE_DATA_LSB        16
 #define CQSPI_REG_RD_INSTR_MODE_EN_LSB          20
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
index fb90532217..34cacf1880 100644
--- a/drivers/spi/cadence_qspi_apb.c
+++ b/drivers/spi/cadence_qspi_apb.c
@@ -446,6 +446,7 @@  int cadence_qspi_apb_command_read_setup(struct cadence_spi_priv *priv,
 		return ret;
 
 	reg = cadence_qspi_calc_rdreg(priv);
+	reg |= op->cmd.dtr ? CQSPI_REG_RD_INSTR_DDR_EN_MASK : 0;
 	writel(reg, priv->regbase + CQSPI_REG_RD_INSTR);
 
 	return 0;
@@ -537,6 +538,7 @@  int cadence_qspi_apb_command_write_setup(struct cadence_spi_priv *priv,
 		return ret;
 
 	reg = cadence_qspi_calc_rdreg(priv);
+	reg |= op->cmd.dtr ? CQSPI_REG_RD_INSTR_DDR_EN_MASK : 0;
 	writel(reg, priv->regbase + CQSPI_REG_RD_INSTR);
 
 	return 0;
@@ -638,6 +640,7 @@  int cadence_qspi_apb_read_setup(struct cadence_spi_priv *priv,
 		opcode = op->cmd.opcode;
 
 	rd_reg = opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
+	rd_reg |= op->cmd.dtr ? CQSPI_REG_RD_INSTR_DDR_EN_MASK : 0;
 	rd_reg |= cadence_qspi_calc_rdreg(priv);
 
 	writel(op->addr.val, priv->regbase + CQSPI_REG_INDIRECTRDSTARTADDR);
@@ -812,6 +815,7 @@  int cadence_qspi_apb_write_setup(struct cadence_spi_priv *priv,
 	writel(reg, priv->regbase + CQSPI_REG_WR_INSTR);
 
 	reg = cadence_qspi_calc_rdreg(priv);
+	reg |= op->cmd.dtr ? CQSPI_REG_RD_INSTR_DDR_EN_MASK : 0;
 	writel(reg, priv->regbase + CQSPI_REG_RD_INSTR);
 
 	writel(op->addr.val, priv->regbase + CQSPI_REG_INDIRECTWRSTARTADDR);