diff mbox series

[1/4] arm: dts: rockchip: rk3566: Remove unnecessary clks from rgxx3

Message ID 20240205185855.21508-2-macroalpha82@gmail.com
State Accepted
Commit c8545d2bba368feaf317d17df08ab5d780b27326
Delegated to: Kever Yang
Headers show
Series Add New Devices for RGxx3 | expand

Commit Message

Chris Morgan Feb. 5, 2024, 6:58 p.m. UTC 
From: Chris Morgan <macromorgan@hotmail.com>

Remove unnecessary clock frequency defines from the RGxx3 u-boot dts.
Move the necessary defines to the RGxx3 main dts file.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
---
 .../arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 31 -------------------
 arch/arm/dts/rk3566-anbernic-rgxx3.dts        |  7 +++++
 2 files changed, 7 insertions(+), 31 deletions(-)

Comments

Kever Yang Feb. 6, 2024, 2:38 a.m. UTC | #1 
Hi Chris,

On 2024/2/6 02:58, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Remove unnecessary clock frequency defines from the RGxx3 u-boot dts.
> Move the necessary defines to the RGxx3 main dts file.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>

First of all, the dts should follow the one in mainline kernel;

and why you need to over write the cru in U-Boot for this board, I 
didn't see this change

in other boards.


Thanks,

- Kever

> ---
>   .../arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 31 -------------------
>   arch/arm/dts/rk3566-anbernic-rgxx3.dts        |  7 +++++
>   2 files changed, 7 insertions(+), 31 deletions(-)
>
> diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
> index f986e1941e..ef4f81500b 100644
> --- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
> +++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
> @@ -15,37 +15,6 @@
>   	};
>   };
>   
> -&cru {
> -	assigned-clocks =
> -			<&pmucru CLK_RTC_32K>,
> -			<&pmucru PLL_PPLL>,
> -			<&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
> -			<&cru PLL_GPLL>,
> -			<&cru ACLK_BUS>, <&cru PCLK_BUS>,
> -			<&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
> -			<&cru HCLK_TOP>, <&cru PCLK_TOP>,
> -			<&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
> -			<&cru CPLL_500M>, <&cru CPLL_333M>,
> -			<&cru CPLL_250M>, <&cru CPLL_125M>,
> -			<&cru CPLL_100M>, <&cru CPLL_62P5M>,
> -			<&cru CPLL_50M>, <&cru CPLL_25M>;
> -		assigned-clock-rates =
> -			<32768>,
> -			<200000000>,
> -			<100000000>, <1000000000>,
> -			<1188000000>,
> -			<150000000>, <100000000>,
> -			<500000000>, <400000000>,
> -			<150000000>, <100000000>,
> -			<300000000>, <150000000>,
> -			<500000000>, <333333333>,
> -			<250000000>, <125000000>,
> -			<100000000>, <62500000>,
> -			<50000000>, <25000000>;
> -		assigned-clock-parents =
> -			<&pmucru CLK_RTC32K_FRAC>;
> -};
> -
>   &dsi_dphy0 {
>   	status = "okay";
>   };
> diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> index 404dddfafb..9e0aa9e63b 100644
> --- a/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> +++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> @@ -16,3 +16,10 @@
>   		     "anbernic,rg353v", "anbernic,rg353vs",
>   		     "anbernic,rg503", "rockchip,rk3566";
>   };
> +
> +&cru {
> +	assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
> +			  <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
> +	assigned-clock-rates = <32768>, <1200000000>,
> +			       <200000000>, <241500000>;
> +};
Chris Morgan Feb. 6, 2024, 3:20 a.m. UTC | #2 
On Tue, Feb 06, 2024 at 10:38:40AM +0800, Kever Yang wrote:
> Hi Chris,
> 
> On 2024/2/6 02:58, Chris Morgan wrote:
> > From: Chris Morgan <macromorgan@hotmail.com>
> > 
> > Remove unnecessary clock frequency defines from the RGxx3 u-boot dts.
> > Move the necessary defines to the RGxx3 main dts file.
> > 
> > Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
> 
> First of all, the dts should follow the one in mainline kernel;
> 
> and why you need to over write the cru in U-Boot for this board, I didn't
> see this change
> 
> in other boards.

This is kind of a special case, because these devices are so similar
they can all use the same bootloader. So as a result I have all 11
of them (and counting) pretending to be a "pseudo" device in U-Boot
called the RGxx3. The only reason I'm setting the clock here is to
set the PLL_VPLL value to something so I can start addressing the
DSI panel. This way, I'm able to probe it and send a panel ID request.
The problem is the manufacturer (Anbernic) has 2 versions of devices
with no distinguishing characteristics.

The specific ask here though is to simplify the clock definition. When
mainlining a different device (the Powkiddy X55) I was asked to not
define so many clocks, especially if they weren't like that in
mainline. It turns out this device also does not need so many
definitions, so this specific patch is to undo them and make it more
simple.

Let me know if you have any other questions. Thank you.
Chris

> 
> 
> Thanks,
> 
> - Kever
> 
> > ---
> >   .../arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 31 -------------------
> >   arch/arm/dts/rk3566-anbernic-rgxx3.dts        |  7 +++++
> >   2 files changed, 7 insertions(+), 31 deletions(-)
> > 
> > diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
> > index f986e1941e..ef4f81500b 100644
> > --- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
> > +++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
> > @@ -15,37 +15,6 @@
> >   	};
> >   };
> > -&cru {
> > -	assigned-clocks =
> > -			<&pmucru CLK_RTC_32K>,
> > -			<&pmucru PLL_PPLL>,
> > -			<&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
> > -			<&cru PLL_GPLL>,
> > -			<&cru ACLK_BUS>, <&cru PCLK_BUS>,
> > -			<&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
> > -			<&cru HCLK_TOP>, <&cru PCLK_TOP>,
> > -			<&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
> > -			<&cru CPLL_500M>, <&cru CPLL_333M>,
> > -			<&cru CPLL_250M>, <&cru CPLL_125M>,
> > -			<&cru CPLL_100M>, <&cru CPLL_62P5M>,
> > -			<&cru CPLL_50M>, <&cru CPLL_25M>;
> > -		assigned-clock-rates =
> > -			<32768>,
> > -			<200000000>,
> > -			<100000000>, <1000000000>,
> > -			<1188000000>,
> > -			<150000000>, <100000000>,
> > -			<500000000>, <400000000>,
> > -			<150000000>, <100000000>,
> > -			<300000000>, <150000000>,
> > -			<500000000>, <333333333>,
> > -			<250000000>, <125000000>,
> > -			<100000000>, <62500000>,
> > -			<50000000>, <25000000>;
> > -		assigned-clock-parents =
> > -			<&pmucru CLK_RTC32K_FRAC>;
> > -};
> > -
> >   &dsi_dphy0 {
> >   	status = "okay";
> >   };
> > diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> > index 404dddfafb..9e0aa9e63b 100644
> > --- a/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> > +++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> > @@ -16,3 +16,10 @@
> >   		     "anbernic,rg353v", "anbernic,rg353vs",
> >   		     "anbernic,rg503", "rockchip,rk3566";
> >   };
> > +
> > +&cru {
> > +	assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
> > +			  <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
> > +	assigned-clock-rates = <32768>, <1200000000>,
> > +			       <200000000>, <241500000>;
> > +};
Kever Yang March 14, 2024, 6:51 a.m. UTC | #3 
On 2024/2/6 02:58, Chris Morgan wrote:
> From: Chris Morgan <macromorgan@hotmail.com>
>
> Remove unnecessary clock frequency defines from the RGxx3 u-boot dts.
> Move the necessary defines to the RGxx3 main dts file.
>
> Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>   .../arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi | 31 -------------------
>   arch/arm/dts/rk3566-anbernic-rgxx3.dts        |  7 +++++
>   2 files changed, 7 insertions(+), 31 deletions(-)
>
> diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
> index f986e1941e..ef4f81500b 100644
> --- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
> +++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
> @@ -15,37 +15,6 @@
>   	};
>   };
>   
> -&cru {
> -	assigned-clocks =
> -			<&pmucru CLK_RTC_32K>,
> -			<&pmucru PLL_PPLL>,
> -			<&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
> -			<&cru PLL_GPLL>,
> -			<&cru ACLK_BUS>, <&cru PCLK_BUS>,
> -			<&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
> -			<&cru HCLK_TOP>, <&cru PCLK_TOP>,
> -			<&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
> -			<&cru CPLL_500M>, <&cru CPLL_333M>,
> -			<&cru CPLL_250M>, <&cru CPLL_125M>,
> -			<&cru CPLL_100M>, <&cru CPLL_62P5M>,
> -			<&cru CPLL_50M>, <&cru CPLL_25M>;
> -		assigned-clock-rates =
> -			<32768>,
> -			<200000000>,
> -			<100000000>, <1000000000>,
> -			<1188000000>,
> -			<150000000>, <100000000>,
> -			<500000000>, <400000000>,
> -			<150000000>, <100000000>,
> -			<300000000>, <150000000>,
> -			<500000000>, <333333333>,
> -			<250000000>, <125000000>,
> -			<100000000>, <62500000>,
> -			<50000000>, <25000000>;
> -		assigned-clock-parents =
> -			<&pmucru CLK_RTC32K_FRAC>;
> -};
> -
>   &dsi_dphy0 {
>   	status = "okay";
>   };
> diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> index 404dddfafb..9e0aa9e63b 100644
> --- a/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> +++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
> @@ -16,3 +16,10 @@
>   		     "anbernic,rg353v", "anbernic,rg353vs",
>   		     "anbernic,rg503", "rockchip,rk3566";
>   };
> +
> +&cru {
> +	assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
> +			  <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
> +	assigned-clock-rates = <32768>, <1200000000>,
> +			       <200000000>, <241500000>;
> +};
diff mbox series

Patch

diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
index f986e1941e..ef4f81500b 100644
--- a/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
+++ b/arch/arm/dts/rk3566-anbernic-rgxx3-u-boot.dtsi
@@ -15,37 +15,6 @@ 
 	};
 };
 
-&cru {
-	assigned-clocks =
-			<&pmucru CLK_RTC_32K>,
-			<&pmucru PLL_PPLL>,
-			<&pmucru PCLK_PMU>, <&cru PLL_CPLL>,
-			<&cru PLL_GPLL>,
-			<&cru ACLK_BUS>, <&cru PCLK_BUS>,
-			<&cru ACLK_TOP_HIGH>, <&cru ACLK_TOP_LOW>,
-			<&cru HCLK_TOP>, <&cru PCLK_TOP>,
-			<&cru ACLK_PERIMID>, <&cru HCLK_PERIMID>,
-			<&cru CPLL_500M>, <&cru CPLL_333M>,
-			<&cru CPLL_250M>, <&cru CPLL_125M>,
-			<&cru CPLL_100M>, <&cru CPLL_62P5M>,
-			<&cru CPLL_50M>, <&cru CPLL_25M>;
-		assigned-clock-rates =
-			<32768>,
-			<200000000>,
-			<100000000>, <1000000000>,
-			<1188000000>,
-			<150000000>, <100000000>,
-			<500000000>, <400000000>,
-			<150000000>, <100000000>,
-			<300000000>, <150000000>,
-			<500000000>, <333333333>,
-			<250000000>, <125000000>,
-			<100000000>, <62500000>,
-			<50000000>, <25000000>;
-		assigned-clock-parents =
-			<&pmucru CLK_RTC32K_FRAC>;
-};
-
 &dsi_dphy0 {
 	status = "okay";
 };
diff --git a/arch/arm/dts/rk3566-anbernic-rgxx3.dts b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
index 404dddfafb..9e0aa9e63b 100644
--- a/arch/arm/dts/rk3566-anbernic-rgxx3.dts
+++ b/arch/arm/dts/rk3566-anbernic-rgxx3.dts
@@ -16,3 +16,10 @@ 
 		     "anbernic,rg353v", "anbernic,rg353vs",
 		     "anbernic,rg503", "rockchip,rk3566";
 };
+
+&cru {
+	assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
+			  <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
+	assigned-clock-rates = <32768>, <1200000000>,
+			       <200000000>, <241500000>;
+};