| Message ID | 20240123171633.246057-5-clamor95@gmail.com |
|---|---|
| State | Accepted |
| Commit | b9ef623c1145c3897deef009c860c0576bc6a310 |
| Delegated to: | Anatolij Gustschin |
| Headers | show |
| Series | Add T114 video support | expand |
On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > Tegra SoC has 2 independent display controllers called DC_A and > DC_B, they are handled differently by internal video devices like > DSI and HDMI controllers so it is important for last to know > which display controller is used to properly set up registers. > To achieve this, a pipe field was added to pdata to pass display > controller id to internal Tegra SoC devices. > > Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 > Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 > Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565 > Tested-by: Ion Agorria <ion@agorria.com> # HTC One X > Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> > --- > drivers/video/tegra20/tegra-dc.c | 6 ++++++ > drivers/video/tegra20/tegra-dc.h | 3 +++ > 2 files changed, 9 insertions(+) > > diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c > index 5d8874f323..0e94e665ef 100644 > --- a/drivers/video/tegra20/tegra-dc.c > +++ b/drivers/video/tegra20/tegra-dc.c > @@ -45,6 +45,7 @@ struct tegra_lcd_priv { > unsigned pixel_clock; /* Pixel clock in Hz */ > int dc_clk[2]; /* Contains clk and its parent */ > bool rotation; /* 180 degree panel turn */ > + bool pipe; /* DC controller: 0 for A, 1 for B */ Bool is a poor choice, even if there's only two of them. This is a proper index, so it should be some sort of integer. Also, the device tree bindings for the display controller specify a "nvidia,head" property that can be used to identify these. If you add that to the U-Boot DT you can avoid looking up by name to map this value. Thierry
пт, 19 квіт. 2024 р. о 19:38 Thierry Reding <thierry.reding@gmail.com> пише: > > On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > > Tegra SoC has 2 independent display controllers called DC_A and > > DC_B, they are handled differently by internal video devices like > > DSI and HDMI controllers so it is important for last to know > > which display controller is used to properly set up registers. > > To achieve this, a pipe field was added to pdata to pass display > > controller id to internal Tegra SoC devices. > > > > Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 > > Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 > > Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565 > > Tested-by: Ion Agorria <ion@agorria.com> # HTC One X > > Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> > > --- > > drivers/video/tegra20/tegra-dc.c | 6 ++++++ > > drivers/video/tegra20/tegra-dc.h | 3 +++ > > 2 files changed, 9 insertions(+) > > > > diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c > > index 5d8874f323..0e94e665ef 100644 > > --- a/drivers/video/tegra20/tegra-dc.c > > +++ b/drivers/video/tegra20/tegra-dc.c > > @@ -45,6 +45,7 @@ struct tegra_lcd_priv { > > unsigned pixel_clock; /* Pixel clock in Hz */ > > int dc_clk[2]; /* Contains clk and its parent */ > > bool rotation; /* 180 degree panel turn */ > > + bool pipe; /* DC controller: 0 for A, 1 for B */ > > Bool is a poor choice, even if there's only two of them. This is a > proper index, so it should be some sort of integer. > > Also, the device tree bindings for the display controller specify a > "nvidia,head" property that can be used to identify these. If you add > that to the U-Boot DT you can avoid looking up by name to map this > value. > Thanks for pointing to this property. May we apply this patch set as is since it is well tested and confirmed to work and I will prepare a follow up patches to adjust device tree relations? Would what be ok? > Thierry
On Fri Apr 19, 2024 at 6:44 PM CEST, Svyatoslav Ryhel wrote: > пт, 19 квіт. 2024 р. о 19:38 Thierry Reding <thierry.reding@gmail.com> пише: > > > > On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > > > Tegra SoC has 2 independent display controllers called DC_A and > > > DC_B, they are handled differently by internal video devices like > > > DSI and HDMI controllers so it is important for last to know > > > which display controller is used to properly set up registers. > > > To achieve this, a pipe field was added to pdata to pass display > > > controller id to internal Tegra SoC devices. > > > > > > Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 > > > Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 > > > Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565 > > > Tested-by: Ion Agorria <ion@agorria.com> # HTC One X > > > Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 > > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> > > > --- > > > drivers/video/tegra20/tegra-dc.c | 6 ++++++ > > > drivers/video/tegra20/tegra-dc.h | 3 +++ > > > 2 files changed, 9 insertions(+) > > > > > > diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c > > > index 5d8874f323..0e94e665ef 100644 > > > --- a/drivers/video/tegra20/tegra-dc.c > > > +++ b/drivers/video/tegra20/tegra-dc.c > > > @@ -45,6 +45,7 @@ struct tegra_lcd_priv { > > > unsigned pixel_clock; /* Pixel clock in Hz */ > > > int dc_clk[2]; /* Contains clk and its parent */ > > > bool rotation; /* 180 degree panel turn */ > > > + bool pipe; /* DC controller: 0 for A, 1 for B */ > > > > Bool is a poor choice, even if there's only two of them. This is a > > proper index, so it should be some sort of integer. > > > > Also, the device tree bindings for the display controller specify a > > "nvidia,head" property that can be used to identify these. If you add > > that to the U-Boot DT you can avoid looking up by name to map this > > value. > > > > Thanks for pointing to this property. May we apply this patch set as is > since it is well tested and confirmed to work and I will prepare a follow > up patches to adjust device tree relations? Would what be ok? Well, there's a few other things that I think should be addressed, but if you'd like to keep this one patch as-is and clean this up later, I guess that's fine. Thierry
пт, 19 квіт. 2024 р. о 19:58 Thierry Reding <thierry.reding@gmail.com> пише: > > On Fri Apr 19, 2024 at 6:44 PM CEST, Svyatoslav Ryhel wrote: > > пт, 19 квіт. 2024 р. о 19:38 Thierry Reding <thierry.reding@gmail.com> пише: > > > > > > On Tue Jan 23, 2024 at 6:16 PM CET, Svyatoslav Ryhel wrote: > > > > Tegra SoC has 2 independent display controllers called DC_A and > > > > DC_B, they are handled differently by internal video devices like > > > > DSI and HDMI controllers so it is important for last to know > > > > which display controller is used to properly set up registers. > > > > To achieve this, a pipe field was added to pdata to pass display > > > > controller id to internal Tegra SoC devices. > > > > > > > > Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 > > > > Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 > > > > Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS Grouper E1565 > > > > Tested-by: Ion Agorria <ion@agorria.com> # HTC One X > > > > Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # Nvidia Tegratab T114 > > > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> > > > > --- > > > > drivers/video/tegra20/tegra-dc.c | 6 ++++++ > > > > drivers/video/tegra20/tegra-dc.h | 3 +++ > > > > 2 files changed, 9 insertions(+) > > > > > > > > diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c > > > > index 5d8874f323..0e94e665ef 100644 > > > > --- a/drivers/video/tegra20/tegra-dc.c > > > > +++ b/drivers/video/tegra20/tegra-dc.c > > > > @@ -45,6 +45,7 @@ struct tegra_lcd_priv { > > > > unsigned pixel_clock; /* Pixel clock in Hz */ > > > > int dc_clk[2]; /* Contains clk and its parent */ > > > > bool rotation; /* 180 degree panel turn */ > > > > + bool pipe; /* DC controller: 0 for A, 1 for B */ > > > > > > Bool is a poor choice, even if there's only two of them. This is a > > > proper index, so it should be some sort of integer. > > > > > > Also, the device tree bindings for the display controller specify a > > > "nvidia,head" property that can be used to identify these. If you add > > > that to the U-Boot DT you can avoid looking up by name to map this > > > value. > > > > > > > Thanks for pointing to this property. May we apply this patch set as is > > since it is well tested and confirmed to work and I will prepare a follow > > up patches to adjust device tree relations? Would what be ok? > > Well, there's a few other things that I think should be addressed, but > if you'd like to keep this one patch as-is and clean this up later, I > guess that's fine. May you send me a list of stuff which you think may be improved? I would gladly adjust whatever I can in follow up. > Thierry
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c index 5d8874f323..0e94e665ef 100644 --- a/drivers/video/tegra20/tegra-dc.c +++ b/drivers/video/tegra20/tegra-dc.c @@ -45,6 +45,7 @@ struct tegra_lcd_priv { unsigned pixel_clock; /* Pixel clock in Hz */ int dc_clk[2]; /* Contains clk and its parent */ bool rotation; /* 180 degree panel turn */ + bool pipe; /* DC controller: 0 for A, 1 for B */ }; enum { @@ -406,6 +407,9 @@ static int tegra_lcd_of_to_plat(struct udevice *dev) priv->rotation = dev_read_bool(dev, "nvidia,180-rotation"); + if (!strcmp(dev->name, TEGRA_DC_B)) + priv->pipe = 1; + rgb = fdt_subnode_offset(blob, node, "rgb"); if (rgb < 0) { debug("%s: Cannot find rgb subnode for '%s' (ret=%d)\n", @@ -431,12 +435,14 @@ static int tegra_lcd_of_to_plat(struct udevice *dev) return ret; } + /* Fill the platform data for internal devices */ if (!strcmp(priv->panel->name, TEGRA_DSI_A) || !strcmp(priv->panel->name, TEGRA_DSI_B)) { struct tegra_dc_plat *dc_plat = dev_get_plat(priv->panel); dc_plat->dev = dev; dc_plat->dc = priv->dc; + dc_plat->pipe = priv->pipe; } ret = panel_get_display_timing(priv->panel, &priv->timing); diff --git a/drivers/video/tegra20/tegra-dc.h b/drivers/video/tegra20/tegra-dc.h index 5c05221038..75fc0fa4de 100644 --- a/drivers/video/tegra20/tegra-dc.h +++ b/drivers/video/tegra20/tegra-dc.h @@ -14,12 +14,15 @@ /* arch-tegra/dc exists only because T124 uses it */ #include <asm/arch-tegra/dc.h> +#define TEGRA_DC_A "dc@54200000" +#define TEGRA_DC_B "dc@54240000" #define TEGRA_DSI_A "dsi@54300000" #define TEGRA_DSI_B "dsi@54400000" struct tegra_dc_plat { struct udevice *dev; /* Display controller device */ struct dc_ctlr *dc; /* Display controller regmap */ + bool pipe; /* DC number: 0 for A, 1 for B */ }; /* This holds information about a window which can be displayed */