| Message ID | 20231027004430.442136-1-judge.packham@gmail.com |
|---|---|
| State | Accepted |
| Commit | cb71a30857db25ccfa96c144f434a370814e74a7 |
| Delegated to: | Stefan Roese |
| Headers | show |
| Series | arm: mvebu: AC5: Use finer grained memory map | expand |
On Fri, Oct 27, 2023 at 01:44:11PM +1300, Chris Packham wrote: > The ATF implementation for AC5/AC5X ends up with bl31 living in some > internal SRAM. This is in the middle of the large MMIO region that we > were using. Adjust this to be finer grained blocks based on the address > map from the AC5X Family Control and Management Subsystem Functional > Datasheet. > > Signed-off-by: Chris Packham <judge.packham@gmail.com> Does this mean we don't need to revert that other patch, or is this unrelated? Thanks.
Hi Tom, On Fri, 27 Oct 2023, 1:54 pm Tom Rini, <trini@konsulko.com> wrote: > On Fri, Oct 27, 2023 at 01:44:11PM +1300, Chris Packham wrote: > > > The ATF implementation for AC5/AC5X ends up with bl31 living in some > > internal SRAM. This is in the middle of the large MMIO region that we > > were using. Adjust this to be finer grained blocks based on the address > > map from the AC5X Family Control and Management Subsystem Functional > > Datasheet. > > > > Signed-off-by: Chris Packham <judge.packham@gmail.com> > > Does this mean we don't need to revert that other patch, or is this > unrelated? Thanks. > Unrelated. Just something I found along the way. I had hope it would fix the hang but with or without this change the HAFDBS support causes issues for me. >
On 10/27/23 02:44, Chris Packham wrote: > The ATF implementation for AC5/AC5X ends up with bl31 living in some > internal SRAM. This is in the middle of the large MMIO region that we > were using. Adjust this to be finer grained blocks based on the address > map from the AC5X Family Control and Management Subsystem Functional > Datasheet. > > Signed-off-by: Chris Packham <judge.packham@gmail.com> Applied to u-boot-marvell/master Thanks, Stefan > --- > > arch/arm/mach-mvebu/alleycat5/cpu.c | 66 ++++++++++++++++++++++------- > 1 file changed, 51 insertions(+), 15 deletions(-) > > diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c > index 8204d9627515..0f72ae1709be 100644 > --- a/arch/arm/mach-mvebu/alleycat5/cpu.c > +++ b/arch/arm/mach-mvebu/alleycat5/cpu.c > @@ -16,7 +16,10 @@ > > DECLARE_GLOBAL_DATA_PTR; > > -#define RAM_SIZE SZ_1G > +#define AC5_PTE_BLOCK_DEVICE \ > + (PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | \ > + PTE_BLOCK_NON_SHARE | \ > + PTE_BLOCK_PXN | PTE_BLOCK_UXN) > > static struct mm_region ac5_mem_map[] = { > { > @@ -31,30 +34,63 @@ static struct mm_region ac5_mem_map[] = { > .phys = 0x00000000, > .virt = 0xa0000000, > .size = 0x100000, > - > - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > - PTE_BLOCK_NON_SHARE | > - PTE_BLOCK_PXN | PTE_BLOCK_UXN > + .attrs = AC5_PTE_BLOCK_DEVICE, > }, > { > /* MMIO regions */ > .phys = 0x100000, > .virt = 0x100000, > .size = 0x3ff00000, > - > - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > - PTE_BLOCK_NON_SHARE | > - PTE_BLOCK_PXN | PTE_BLOCK_UXN > + .attrs = AC5_PTE_BLOCK_DEVICE, > }, > { > - /* MMIO regions */ > .phys = 0x7F000000, > .virt = 0x7F000000, > - .size = 0x21000000, > - > - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > - PTE_BLOCK_NON_SHARE | > - PTE_BLOCK_PXN | PTE_BLOCK_UXN > + .size = SZ_8M, > + .attrs = AC5_PTE_BLOCK_DEVICE, > + }, > + { > + .phys = 0x7F800000, > + .virt = 0x7F800000, > + .size = SZ_4M, > + .attrs = AC5_PTE_BLOCK_DEVICE, > + }, > + { > + .phys = 0x7FC00000, > + .virt = 0x7FC00000, > + .size = SZ_512K, > + .attrs = AC5_PTE_BLOCK_DEVICE, > + }, > + { > + .phys = 0x7FC80000, > + .virt = 0x7FC80000, > + .size = SZ_512K, > + .attrs = AC5_PTE_BLOCK_DEVICE, > + }, > + { > + .phys = 0x7FD00000, > + .virt = 0x7FD00000, > + .size = SZ_512K, > + .attrs = AC5_PTE_BLOCK_DEVICE, > + }, > + /* ATF region 0x7FE00000-0x7FE20000 not mapped */ > + { > + .phys = 0x7FE80000, > + .virt = 0x7FE80000, > + .size = SZ_512K, > + .attrs = AC5_PTE_BLOCK_DEVICE, > + }, > + { > + .phys = 0x7FFF0000, > + .virt = 0x7FFF0000, > + .size = SZ_1M, > + .attrs = AC5_PTE_BLOCK_DEVICE, > + }, > + { > + .phys = 0x80000000, > + .virt = 0x80000000, > + .size = SZ_2G, > + .attrs = AC5_PTE_BLOCK_DEVICE, > }, > { > 0, Viele Grüße, Stefan Roese
diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c index 8204d9627515..0f72ae1709be 100644 --- a/arch/arm/mach-mvebu/alleycat5/cpu.c +++ b/arch/arm/mach-mvebu/alleycat5/cpu.c @@ -16,7 +16,10 @@ DECLARE_GLOBAL_DATA_PTR; -#define RAM_SIZE SZ_1G +#define AC5_PTE_BLOCK_DEVICE \ + (PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | \ + PTE_BLOCK_NON_SHARE | \ + PTE_BLOCK_PXN | PTE_BLOCK_UXN) static struct mm_region ac5_mem_map[] = { { @@ -31,30 +34,63 @@ static struct mm_region ac5_mem_map[] = { .phys = 0x00000000, .virt = 0xa0000000, .size = 0x100000, - - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN + .attrs = AC5_PTE_BLOCK_DEVICE, }, { /* MMIO regions */ .phys = 0x100000, .virt = 0x100000, .size = 0x3ff00000, - - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN + .attrs = AC5_PTE_BLOCK_DEVICE, }, { - /* MMIO regions */ .phys = 0x7F000000, .virt = 0x7F000000, - .size = 0x21000000, - - .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | - PTE_BLOCK_NON_SHARE | - PTE_BLOCK_PXN | PTE_BLOCK_UXN + .size = SZ_8M, + .attrs = AC5_PTE_BLOCK_DEVICE, + }, + { + .phys = 0x7F800000, + .virt = 0x7F800000, + .size = SZ_4M, + .attrs = AC5_PTE_BLOCK_DEVICE, + }, + { + .phys = 0x7FC00000, + .virt = 0x7FC00000, + .size = SZ_512K, + .attrs = AC5_PTE_BLOCK_DEVICE, + }, + { + .phys = 0x7FC80000, + .virt = 0x7FC80000, + .size = SZ_512K, + .attrs = AC5_PTE_BLOCK_DEVICE, + }, + { + .phys = 0x7FD00000, + .virt = 0x7FD00000, + .size = SZ_512K, + .attrs = AC5_PTE_BLOCK_DEVICE, + }, + /* ATF region 0x7FE00000-0x7FE20000 not mapped */ + { + .phys = 0x7FE80000, + .virt = 0x7FE80000, + .size = SZ_512K, + .attrs = AC5_PTE_BLOCK_DEVICE, + }, + { + .phys = 0x7FFF0000, + .virt = 0x7FFF0000, + .size = SZ_1M, + .attrs = AC5_PTE_BLOCK_DEVICE, + }, + { + .phys = 0x80000000, + .virt = 0x80000000, + .size = SZ_2G, + .attrs = AC5_PTE_BLOCK_DEVICE, }, { 0,
The ATF implementation for AC5/AC5X ends up with bl31 living in some internal SRAM. This is in the middle of the large MMIO region that we were using. Adjust this to be finer grained blocks based on the address map from the AC5X Family Control and Management Subsystem Functional Datasheet. Signed-off-by: Chris Packham <judge.packham@gmail.com> --- arch/arm/mach-mvebu/alleycat5/cpu.c | 66 ++++++++++++++++++++++------- 1 file changed, 51 insertions(+), 15 deletions(-)