| Message ID | 20230928215455.28094-12-andre.przywara@arm.com |
|---|---|
| State | Accepted |
| Delegated to: | Andre Przywara |
| Headers | show |
| Series | sunxi: Allwinner T113s support | expand |
Hi Andre, On 9/28/23 16:54, Andre Przywara wrote: > Apart from using the new pinctrl MMIO register layout, the Allwinner D1 > and related SoCs still need to usual set of mux values hardcoded in > U-Boot's pinctrl driver. > Add the values we need so far to this list, so that DM based drivers > will just work without further ado. > > Signed-off-by: Andre Przywara <andre.przywara@arm.com> > --- > drivers/pinctrl/sunxi/Kconfig | 4 ++++ > drivers/pinctrl/sunxi/pinctrl-sunxi.c | 28 +++++++++++++++++++++++++++ > 2 files changed, 32 insertions(+) > > diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig > index 77da90836b6..c8f937d91e9 100644 > --- a/drivers/pinctrl/sunxi/Kconfig > +++ b/drivers/pinctrl/sunxi/Kconfig > @@ -124,4 +124,8 @@ config PINCTRL_SUN50I_H616_R > default MACH_SUN50I_H616 > select PINCTRL_SUNXI > > +config PINCTRL_SUN20I_D1 > + bool "Support for the Allwinner D1/R528 PIO" > + select PINCTRL_SUNXI > + > endif > diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c > index fc80fe50b14..66876d9954a 100644 > --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c > +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c > @@ -748,6 +748,28 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_r_pinctrl_desc > .num_banks = 1, > }; > > +static const struct sunxi_pinctrl_function sun20i_d1_pinctrl_functions[] = { Please keep these sections (and the OF match data) sorted numerically. > + { "emac", 8 }, /* PE0-PE15 */ > + { "gpio_in", 0 }, > + { "gpio_out", 1 }, My local patch had a few more entries. Feel free to add them: + { "i2c0", 4 }, /* PB10-PB11 */ > + { "mmc0", 2 }, /* PF0-PF5 */ + { "mmc1", 2 }, /* PG0-PG5 */ > + { "mmc2", 3 }, /* PC1-PC7 */ Should be PC2-PC7. Everything else looks correct. > + { "spi0", 2 }, /* PC2-PC7 */ > +#if IS_ENABLED(CONFIG_UART0_PORT_F) > + { "uart0", 3 }, /* PF2,PF4 */ > +#else > + { "uart0", 6 }, /* PB0-PB1, PB8-PB9, PE2-PE3 */ > +#endif + { "uart1", 2 }, /* PG6-PG7 */ + { "uart2", 7 }, /* PB0-PB1 */ Regards, Samuel > + { "uart3", 7 }, /* PB6-PB7 */ > +}; > + > +static const struct sunxi_pinctrl_desc __maybe_unused sun20i_d1_pinctrl_desc = { > + .functions = sun20i_d1_pinctrl_functions, > + .num_functions = ARRAY_SIZE(sun20i_d1_pinctrl_functions), > + .first_bank = SUNXI_GPIO_A, > + .num_banks = 7, > +}; > + > static const struct udevice_id sunxi_pinctrl_ids[] = { > #ifdef CONFIG_PINCTRL_SUNIV_F1C100S > { > @@ -904,6 +926,12 @@ static const struct udevice_id sunxi_pinctrl_ids[] = { > .compatible = "allwinner,sun50i-h616-r-pinctrl", > .data = (ulong)&sun50i_h616_r_pinctrl_desc, > }, > +#endif > +#ifdef CONFIG_PINCTRL_SUN20I_D1 > + { > + .compatible = "allwinner,sun20i-d1-pinctrl", > + .data = (ulong)&sun20i_d1_pinctrl_desc, > + }, > #endif > {} > };
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 77da90836b6..c8f937d91e9 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -124,4 +124,8 @@ config PINCTRL_SUN50I_H616_R default MACH_SUN50I_H616 select PINCTRL_SUNXI +config PINCTRL_SUN20I_D1 + bool "Support for the Allwinner D1/R528 PIO" + select PINCTRL_SUNXI + endif diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index fc80fe50b14..66876d9954a 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -748,6 +748,28 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun50i_h616_r_pinctrl_desc .num_banks = 1, }; +static const struct sunxi_pinctrl_function sun20i_d1_pinctrl_functions[] = { + { "emac", 8 }, /* PE0-PE15 */ + { "gpio_in", 0 }, + { "gpio_out", 1 }, + { "mmc0", 2 }, /* PF0-PF5 */ + { "mmc2", 3 }, /* PC1-PC7 */ + { "spi0", 2 }, /* PC2-PC7 */ +#if IS_ENABLED(CONFIG_UART0_PORT_F) + { "uart0", 3 }, /* PF2,PF4 */ +#else + { "uart0", 6 }, /* PB0-PB1, PB8-PB9, PE2-PE3 */ +#endif + { "uart3", 7 }, /* PB6-PB7 */ +}; + +static const struct sunxi_pinctrl_desc __maybe_unused sun20i_d1_pinctrl_desc = { + .functions = sun20i_d1_pinctrl_functions, + .num_functions = ARRAY_SIZE(sun20i_d1_pinctrl_functions), + .first_bank = SUNXI_GPIO_A, + .num_banks = 7, +}; + static const struct udevice_id sunxi_pinctrl_ids[] = { #ifdef CONFIG_PINCTRL_SUNIV_F1C100S { @@ -904,6 +926,12 @@ static const struct udevice_id sunxi_pinctrl_ids[] = { .compatible = "allwinner,sun50i-h616-r-pinctrl", .data = (ulong)&sun50i_h616_r_pinctrl_desc, }, +#endif +#ifdef CONFIG_PINCTRL_SUN20I_D1 + { + .compatible = "allwinner,sun20i-d1-pinctrl", + .data = (ulong)&sun20i_d1_pinctrl_desc, + }, #endif {} };
Apart from using the new pinctrl MMIO register layout, the Allwinner D1 and related SoCs still need to usual set of mux values hardcoded in U-Boot's pinctrl driver. Add the values we need so far to this list, so that DM based drivers will just work without further ado. Signed-off-by: Andre Przywara <andre.przywara@arm.com> --- drivers/pinctrl/sunxi/Kconfig | 4 ++++ drivers/pinctrl/sunxi/pinctrl-sunxi.c | 28 +++++++++++++++++++++++++++ 2 files changed, 32 insertions(+)