| Message ID | 20230817015149.774847-5-sjg@chromium.org |
|---|---|
| State | Superseded |
| Delegated to: | Bin Meng |
| Headers | show |
| Series | x86: Fixes and improvements for coreboot | expand |
diff --git a/configs/coreboot64_defconfig b/configs/coreboot64_defconfig index 55064d1ce66f..9f228420cfa9 100644 --- a/configs/coreboot64_defconfig +++ b/configs/coreboot64_defconfig @@ -55,5 +55,6 @@ CONFIG_SYS_64BIT_LBA=y CONFIG_SOUND=y CONFIG_SOUND_I8254=y CONFIG_CONSOLE_SCROLL_LINES=5 +CONFIG_SPL_ACPI=y # CONFIG_GZIP is not set CONFIG_CMD_CBFS=y diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 7ca42df6a7e2..27b4b9d96507 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -672,7 +672,7 @@ config COREBOOT_SERIAL config COREBOOT_SERIAL_FROM_DBG2 bool "Obtain UART from ACPI tables" depends on COREBOOT_SERIAL - default y if !SPL + default y help Select this to try to find a DBG2 record in the ACPI tables, in the event that coreboot does not provide information about the UART in the
If coreboot does not set up sysinfo for the UART, SPL currently hangs. Use the DBG2 teechnique there as well. This allows coreboot64 to boot from coreboot even if the console info is missing from sysinfo Signed-off-by: Simon Glass <sjg@chromium.org> --- configs/coreboot64_defconfig | 1 + drivers/serial/Kconfig | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-)