| Message ID | 20230627012456.3899052-1-bmeng@tinylab.org |
|---|---|
| State | Accepted |
| Commit | 4a3efd71cd858b87527e9478ff51529d39329819 |
| Delegated to: | Andes |
| Headers | show |
| Series | [v2] riscv: Fix alignment of RELA sections in the linker scripts | expand |
diff --git a/arch/riscv/cpu/u-boot.lds b/arch/riscv/cpu/u-boot.lds index 15b5cbc585..2ffe6ba3c8 100644 --- a/arch/riscv/cpu/u-boot.lds +++ b/arch/riscv/cpu/u-boot.lds @@ -48,7 +48,7 @@ SECTIONS KEEP(*(SORT(__u_boot_list*))); } - . = ALIGN(4); + . = ALIGN(8); .efi_runtime_rel : { __efi_runtime_rel_start = .; @@ -57,8 +57,6 @@ SECTIONS __efi_runtime_rel_stop = .; } - . = ALIGN(8); - /DISCARD/ : { *(.rela.plt*) } .rela.dyn : { __rel_dyn_start = .;
In current linker script both .efi_runtime_rel and .rela.dyn sections are of RELA type whose entry size is either 12 (RV32) or 24 (RV64). These two are arranged as a continuous region on purpose so that the prelink-riscv executable can fix up the PIE addresses in one loop. However there is an 'ALIGN(8)' between these 2 sections which might cause a gap to be inserted between these 2 sections to satisfy the alignment requirement on RV32. This would break the assumption of the prelink process and generate an unbootable image. Fixes: 9a6569a043d3 ("riscv: Update alignment for some sections in linker scripts") Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com> --- Changes in v2: - fix typos in the commit message arch/riscv/cpu/u-boot.lds | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)