[v1,2/3] riscv: dts: sync mpfs-icicle devicetree with linux

The "notable" disappearances are:
- the pac193x stanza - there's nothing in mainline linux w.r.t. bindings
  for this & what is going to appear in mainline linux is going to be
  incompatible with what is currently in U-Boot.
- operating points - these operating points should not be set at the
  soc.dtsi level as they may not be possible depending on the design
  programmed to the FPGA
- clock output names - there are defines for the clock indices, these
  should not be needed
- the dt maintainers in linux NAKed using defines for IRQ numbers
- the qspi nand, which is not part of the icicle's default configuration
  is removed.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi    |  71 +++
 arch/riscv/dts/mpfs-icicle-kit.dts            | 190 +++++---
 arch/riscv/dts/mpfs.dtsi                      | 442 ++++++++----------
 .../dt-bindings/clock/microchip-mpfs-clock.h  |  29 +-
 .../microchip-mpfs-plic.h                     | 196 --------
 .../interrupt-controller/riscv-hart.h         |  17 -
 6 files changed, 420 insertions(+), 525 deletions(-)
 create mode 100644 arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
 delete mode 100644 include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h
 delete mode 100644 include/dt-bindings/interrupt-controller/riscv-hart.h

> On Wed, 2023-06-07 at 11:06 +0100, Conor Dooley wrote:
> The "notable" disappearances are:
> - the pac193x stanza - there's nothing in mainline linux w.r.t.
> bindings
>   for this & what is going to appear in mainline linux is going to be
>   incompatible with what is currently in U-Boot.
> - operating points - these operating points should not be set at the
>   soc.dtsi level as they may not be possible depending on the design
>   programmed to the FPGA
> - clock output names - there are defines for the clock indices, these
>   should not be needed
> - the dt maintainers in linux NAKed using defines for IRQ numbers
> - the qspi nand, which is not part of the icicle's default
> configuration
>   is removed.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>  arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi    |  71 +++
>  arch/riscv/dts/mpfs-icicle-kit.dts            | 190 +++++---
>  arch/riscv/dts/mpfs.dtsi                      | 442 ++++++++------
> ----
>  .../dt-bindings/clock/microchip-mpfs-clock.h  |  29 +-
>  .../microchip-mpfs-plic.h                     | 196 --------
>  .../interrupt-controller/riscv-hart.h         |  17 -
>  6 files changed, 420 insertions(+), 525 deletions(-)
>  create mode 100644 arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
>  delete mode 100644 include/dt-bindings/interrupt-
> controller/microchip-mpfs-plic.h
>  delete mode 100644 include/dt-bindings/interrupt-controller/riscv-
> hart.h
> 
Reviewed-by: Padmarao Begari <padmarao.begari@microchip.com>
Tested-by: Padmarao Begari <padmarao.begari@microchip.com>

> diff --git a/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
> b/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
> new file mode 100644
> index 0000000000..1069134f2e
> --- /dev/null
> +++ b/arch/riscv/dts/mpfs-icicle-kit-fabric.dtsi
> @@ -0,0 +1,71 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/* Copyright (c) 2020-2021 Microchip Technology Inc */
> +
> +/ {
> +	compatible = "microchip,mpfs-icicle-reference-rtlv2210",
> "microchip,mpfs-icicle-kit",
> +		     "microchip,mpfs";
> +
> +	core_pwm0: pwm@40000000 {
> +		compatible = "microchip,corepwm-rtl-v4";
> +		reg = <0x0 0x40000000 0x0 0xF0>;
> +		microchip,sync-update-mask = /bits/ 32 <0>;
> +		#pwm-cells = <3>;
> +		clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
> +		status = "disabled";
> +	};
> +
> +	i2c2: i2c@40000200 {
> +		compatible = "microchip,corei2c-rtl-v7";
> +		reg = <0x0 0x40000200 0x0 0x100>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>;
> +		interrupt-parent = <&plic>;
> +		interrupts = <122>;
> +		clock-frequency = <100000>;
> +		status = "disabled";
> +	};
> +
> +	pcie: pcie@3000000000 {
> +		compatible = "microchip,pcie-host-1.0";
> +		#address-cells = <0x3>;
> +		#interrupt-cells = <0x1>;
> +		#size-cells = <0x2>;
> +		device_type = "pci";
> +		reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0
> 0x10000>;
> +		reg-names = "cfg", "apb";
> +		bus-range = <0x0 0x7f>;
> +		interrupt-parent = <&plic>;
> +		interrupts = <119>;
> +		interrupt-map = <0 0 0 1 &pcie_intc 0>,
> +				<0 0 0 2 &pcie_intc 1>,
> +				<0 0 0 3 &pcie_intc 2>,
> +				<0 0 0 4 &pcie_intc 3>;
> +		interrupt-map-mask = <0 0 0 7>;
> +		clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw
> CLK_CCC_PLL0_OUT3>;
> +		clock-names = "fic1", "fic3";
> +		ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0
> 0x80000000>;
> +		dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000
> 0x1 0x00000000>;
> +		msi-parent = <&pcie>;
> +		msi-controller;
> +		status = "disabled";
> +		pcie_intc: interrupt-controller {
> +			#address-cells = <0>;
> +			#interrupt-cells = <1>;
> +			interrupt-controller;
> +		};
> +	};
> +
> +	refclk_ccc: cccrefclk {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +	};
> +};
> +
> +&ccc_nw {
> +	clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
> <&refclk_ccc>,
> +		 <&refclk_ccc>, <&refclk_ccc>;
> +	clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0",
> "pll1_ref1",
> +		      "dll0_ref", "dll1_ref";
> +	status = "okay";
> +};
> diff --git a/arch/riscv/dts/mpfs-icicle-kit.dts
> b/arch/riscv/dts/mpfs-icicle-kit.dts
> index 3c56400b92..8aa5fb17d6 100644
> --- a/arch/riscv/dts/mpfs-icicle-kit.dts
> +++ b/arch/riscv/dts/mpfs-icicle-kit.dts
> @@ -7,29 +7,63 @@
>  /dts-v1/;
>  
>  #include "mpfs.dtsi"
> +#include "mpfs-icicle-kit-fabric.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/leds/common.h>
>  
>  /* Clock frequency (in Hz) of the rtcclk */
>  #define RTCCLK_FREQ		1000000
>  
>  / {
>  	model = "Microchip PolarFire-SoC Icicle Kit";
> -	compatible = "microchip,mpfs-icicle-reference-rtlv2210",
> -		     "microchip,mpfs-icicle-kit", "microchip,mpfs";
> +	compatible = "microchip,mpfs-icicle-reference-rtlv2210",
> "microchip,mpfs-icicle-kit",
> +		     "microchip,mpfs";
>  
>  	aliases {
> -		serial1 = &uart1;
>  		ethernet0 = &mac1;
> -		spi0 = &qspi;
> +		serial0 = &mmuart0;
> +		serial1 = &mmuart1;
> +		serial2 = &mmuart2;
> +		serial3 = &mmuart3;
> +		serial4 = &mmuart4;
>  	};
>  
>  	chosen {
> -		stdout-path = "serial1";
> +		stdout-path = "serial1:115200n8";
>  	};
>  
>  	cpus {
>  		timebase-frequency = <RTCCLK_FREQ>;
>  	};
>  
> +	leds {
> +		compatible = "gpio-leds";
> +
> +		led-1 {
> +			gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
> +			color = <LED_COLOR_ID_RED>;
> +			label = "led1";
> +		};
> +
> +		led-2 {
> +			gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
> +			color = <LED_COLOR_ID_RED>;
> +			label = "led2";
> +		};
> +
> +		led-3 {
> +			gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
> +			color = <LED_COLOR_ID_AMBER>;
> +			label = "led3";
> +		};
> +
> +		led-4 {
> +			gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> +			color = <LED_COLOR_ID_AMBER>;
> +			label = "led4";
> +		};
> +	};
> +
>  	ddrc_cache_lo: memory@80000000 {
>  		device_type = "memory";
>  		reg = <0x0 0x80000000 0x0 0x40000000>;
> @@ -54,83 +88,121 @@
>  	};
>  };
>  
> -&refclk {
> -	clock-frequency = <125000000>;
> +&core_pwm0 {
> +	status = "okay";
>  };
>  
> -&uart1 {
> +&gpio2 {
> +	interrupts = <53>, <53>, <53>, <53>,
> +		     <53>, <53>, <53>, <53>,
> +		     <53>, <53>, <53>, <53>,
> +		     <53>, <53>, <53>, <53>,
> +		     <53>, <53>, <53>, <53>,
> +		     <53>, <53>, <53>, <53>,
> +		     <53>, <53>, <53>, <53>,
> +		     <53>, <53>, <53>, <53>;
> +	status = "okay";
> +};
> +
> +&i2c0 {
> +	status = "okay";
> +};
> +
> +&i2c1 {
> +	status = "okay";
> +};
> +
> +&i2c2 {
> +	status = "okay";
> +};
> +
> +&mac0 {
> +	phy-mode = "sgmii";
> +	phy-handle = <&phy0>;
> +	status = "enabled";
> +};
> +
> +&mac1 {
> +	phy-mode = "sgmii";
> +	phy-handle = <&phy1>;
> +	status = "okay";
> +
> +	phy1: ethernet-phy@9 {
> +		reg = <9>;
> +	};
> +
> +	phy0: ethernet-phy@8 {
> +		reg = <8>;
> +	};
> +};
> +
> +&mbox {
>  	status = "okay";
>  };
>  
>  &mmc {
> -	status = "okay";
> -
>  	bus-width = <4>;
>  	disable-wp;
> -	cap-mmc-highspeed;
>  	cap-sd-highspeed;
> -	card-detect-delay = <200>;
> +	cap-mmc-highspeed;
>  	mmc-ddr-1_8v;
>  	mmc-hs200-1_8v;
>  	sd-uhs-sdr12;
>  	sd-uhs-sdr25;
>  	sd-uhs-sdr50;
>  	sd-uhs-sdr104;
> +	status = "okay";
>  };
>  
> -&i2c1 {
> +&mmuart1 {
>  	status = "okay";
> -	clock-frequency = <100000>;
> -
> -	pac193x: pac193x@10 {
> -		compatible = "microchip,pac1934";
> -		reg = <0x10>;
> -		samp-rate = <64>;
> -		status = "okay";
> -		ch1: channel0 {
> -			uohms-shunt-res = <10000>;
> -			rail-name = "VDDREG";
> -			channel_enabled;
> -		};
> -		ch2: channel1 {
> -			uohms-shunt-res = <10000>;
> -			rail-name = "VDDA25";
> -			channel_enabled;
> -		};
> -		ch3: channel2 {
> -			uohms-shunt-res = <10000>;
> -			rail-name = "VDD25";
> -			channel_enabled;
> -		};
> -		ch4: channel3 {
> -			uohms-shunt-res = <10000>;
> -			rail-name = "VDDA_REG";
> -			channel_enabled;
> -		};
> -	};
>  };
>  
> -&mac1 {
> +&mmuart2 {
> +	status = "okay";
> +};
> +
> +&mmuart3 {
> +	status = "okay";
> +};
> +
> +&mmuart4 {
> +	status = "okay";
> +};
> +
> +&pcie {
>  	status = "okay";
> -	phy-mode = "sgmii";
> -	phy-handle = <&phy1>;
> -	phy1: ethernet-phy@9 {
> -		reg = <9>;
> -		ti,fifo-depth = <0x1>;
> -	};
>  };
>  
>  &qspi {
>  	status = "okay";
> -	num-cs = <1>;
> -
> -	flash0: flash@0 {
> -		compatible = "spi-nand";
> -		reg = <0x0>;
> -		spi-tx-bus-width = <4>;
> -		spi-rx-bus-width = <4>;
> -		spi-max-frequency = <20000000>;
> -		spi-cpol;
> -		spi-cpha;
> -	};
> +};
> +
> +&refclk {
> +	clock-frequency = <125000000>;
> +};
> +
> +&refclk_ccc {
> +	clock-frequency = <50000000>;
> +};
> +
> +&rtc {
> +	status = "okay";
> +};
> +
> +&spi0 {
> +	status = "okay";
> +};
> +
> +&spi1 {
> +	status = "okay";
> +};
> +
> +&syscontroller {
> +	status = "okay";
> +};
> +
> +&usb {
> +	status = "okay";
> +	dr_mode = "host";
>  };
> diff --git a/arch/riscv/dts/mpfs.dtsi b/arch/riscv/dts/mpfs.dtsi
> index 891dd0918b..6012a28507 100644
> --- a/arch/riscv/dts/mpfs.dtsi
> +++ b/arch/riscv/dts/mpfs.dtsi
> @@ -2,8 +2,6 @@
>  /* Copyright (c) 2020-2021 Microchip Technology Inc */
>  
>  #include "dt-bindings/clock/microchip-mpfs-clock.h"
> -#include "dt-bindings/interrupt-controller/microchip-mpfs-plic.h"
> -#include "dt-bindings/interrupt-controller/riscv-hart.h"
>  
>  / {
>  	#address-cells = <2>;
> @@ -11,9 +9,6 @@
>  	model = "Microchip PolarFire SoC";
>  	compatible = "microchip,mpfs";
>  
> -	chosen {
> -	};
> -
>  	cpus {
>  		#address-cells = <1>;
>  		#size-cells = <0>;
> @@ -28,12 +23,7 @@
>  			riscv,isa = "rv64imac";
>  			clocks = <&clkcfg CLK_CPU>;
>  			status = "disabled";
> -			operating-points = <
> -				/* kHz	uV */
> -				600000  1100000
> -				300000   950000
> -				150000   750000
> -			>;
> +
>  			cpu0_intc: interrupt-controller {
>  				#interrupt-cells = <1>;
>  				compatible = "riscv,cpu-intc";
> @@ -59,13 +49,9 @@
>  			riscv,isa = "rv64imafdc";
>  			clocks = <&clkcfg CLK_CPU>;
>  			tlb-split;
> +			next-level-cache = <&cctrllr>;
>  			status = "okay";
> -			operating-points = <
> -				/* kHz	uV */
> -				600000  1100000
> -				300000   950000
> -				150000   750000
> -			>;
> +
>  			cpu1_intc: interrupt-controller {
>  				#interrupt-cells = <1>;
>  				compatible = "riscv,cpu-intc";
> @@ -91,13 +77,9 @@
>  			riscv,isa = "rv64imafdc";
>  			clocks = <&clkcfg CLK_CPU>;
>  			tlb-split;
> +			next-level-cache = <&cctrllr>;
>  			status = "okay";
> -			operating-points = <
> -				/* kHz	uV */
> -				600000  1100000
> -				300000   950000
> -				150000   750000
> -			>;
> +
>  			cpu2_intc: interrupt-controller {
>  				#interrupt-cells = <1>;
>  				compatible = "riscv,cpu-intc";
> @@ -123,13 +105,9 @@
>  			riscv,isa = "rv64imafdc";
>  			clocks = <&clkcfg CLK_CPU>;
>  			tlb-split;
> +			next-level-cache = <&cctrllr>;
>  			status = "okay";
> -			operating-points = <
> -				/* kHz	uV */
> -				600000  1100000
> -				300000   950000
> -				150000   750000
> -			>;
> +
>  			cpu3_intc: interrupt-controller {
>  				#interrupt-cells = <1>;
>  				compatible = "riscv,cpu-intc";
> @@ -155,273 +133,322 @@
>  			riscv,isa = "rv64imafdc";
>  			clocks = <&clkcfg CLK_CPU>;
>  			tlb-split;
> +			next-level-cache = <&cctrllr>;
>  			status = "okay";
> -			operating-points = <
> -				/* kHz	uV */
> -				600000  1100000
> -				300000   950000
> -				150000   750000
> -			>;
>  			cpu4_intc: interrupt-controller {
>  				#interrupt-cells = <1>;
>  				compatible = "riscv,cpu-intc";
>  				interrupt-controller;
>  			};
>  		};
> +
> +		cpu-map {
> +			cluster0 {
> +				core0 {
> +					cpu = <&cpu0>;
> +				};
> +
> +				core1 {
> +					cpu = <&cpu1>;
> +				};
> +
> +				core2 {
> +					cpu = <&cpu2>;
> +				};
> +
> +				core3 {
> +					cpu = <&cpu3>;
> +				};
> +
> +				core4 {
> +					cpu = <&cpu4>;
> +				};
> +			};
> +		};
>  	};
>  
> -	refclk: refclk {
> +	refclk: mssrefclk {
>  		compatible = "fixed-clock";
>  		#clock-cells = <0>;
>  	};
>  
> +	syscontroller: syscontroller {
> +		compatible = "microchip,mpfs-sys-controller";
> +		mboxes = <&mbox 0>;
> +	};
> +
>  	soc {
>  		#address-cells = <2>;
>  		#size-cells = <2>;
> -		compatible = "microchip,mpfs-soc", "simple-bus";
> +		compatible = "simple-bus";
>  		ranges;
>  
> -		clint: clint@2000000 {
> -			compatible = "sifive,clint0";
> -			reg = <0x0 0x2000000 0x0 0xC000>;
> -			interrupts-extended =
> -					<&cpu0_intc HART_INT_M_SOFT
> &cpu0_intc HART_INT_M_TIMER
> -					 &cpu1_intc HART_INT_M_SOFT
> &cpu1_intc HART_INT_M_TIMER
> -					 &cpu2_intc HART_INT_M_SOFT
> &cpu2_intc HART_INT_M_TIMER
> -					 &cpu3_intc HART_INT_M_SOFT
> &cpu3_intc HART_INT_M_TIMER
> -					 &cpu4_intc HART_INT_M_SOFT
> &cpu4_intc HART_INT_M_TIMER>;
> -		};
> -
> -		cachecontroller: cache-controller@2010000 {
> -			compatible = "sifive,fu540-c000-ccache",
> "cache";
> +		cctrllr: cache-controller@2010000 {
> +			compatible = "microchip,mpfs-ccache",
> "sifive,fu540-c000-ccache", "cache";
>  			reg = <0x0 0x2010000 0x0 0x1000>;
> -			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_L2_METADATA_CORR
> -				PLIC_INT_L2_METADATA_UNCORR
> -				PLIC_INT_L2_DATA_CORR>;
>  			cache-block-size = <64>;
>  			cache-level = <2>;
>  			cache-sets = <1024>;
>  			cache-size = <2097152>;
>  			cache-unified;
> +			interrupt-parent = <&plic>;
> +			interrupts = <1>, <3>, <4>, <2>;
>  		};
>  
> -		pdma: pdma@3000000 {
> -			compatible = "microchip,mpfs-pdma-
> uio","sifive,fu540-c000-pdma";
> -			reg = <0x0 0x3000000 0x0 0x8000>;
> -			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_DMA_CH0_DONE
> PLIC_INT_DMA_CH0_ERR
> -				PLIC_INT_DMA_CH1_DONE
> PLIC_INT_DMA_CH1_ERR
> -				PLIC_INT_DMA_CH2_DONE
> PLIC_INT_DMA_CH2_ERR
> -				PLIC_INT_DMA_CH3_DONE
> PLIC_INT_DMA_CH3_ERR>;
> -			#dma-cells = <1>;
> +		clint: clint@2000000 {
> +			compatible = "sifive,fu540-c000-clint",
> "sifive,clint0";
> +			reg = <0x0 0x2000000 0x0 0xC000>;
> +			interrupts-extended = <&cpu0_intc 3>,
> <&cpu0_intc 7>,
> +					      <&cpu1_intc 3>,
> <&cpu1_intc 7>,
> +					      <&cpu2_intc 3>,
> <&cpu2_intc 7>,
> +					      <&cpu3_intc 3>,
> <&cpu3_intc 7>,
> +					      <&cpu4_intc 3>,
> <&cpu4_intc 7>;
>  		};
>  
>  		plic: interrupt-controller@c000000 {
> -			compatible = "sifive,plic-1.0.0";
> +			compatible = "sifive,fu540-c000-plic",
> "sifive,plic-1.0.0";
>  			reg = <0x0 0xc000000 0x0 0x4000000>;
> +			#address-cells = <0>;
>  			#interrupt-cells = <1>;
> -			riscv,ndev = <186>;
>  			interrupt-controller;
> -			interrupts-extended = <&cpu0_intc
> HART_INT_M_EXT
> -					&cpu1_intc HART_INT_M_EXT
> &cpu1_intc HART_INT_S_EXT
> -					&cpu2_intc HART_INT_M_EXT
> &cpu2_intc HART_INT_S_EXT
> -					&cpu3_intc HART_INT_M_EXT
> &cpu3_intc HART_INT_S_EXT
> -					&cpu4_intc HART_INT_M_EXT
> &cpu4_intc HART_INT_S_EXT>;
> +			interrupts-extended = <&cpu0_intc 11>,
> +					      <&cpu1_intc 11>,
> <&cpu1_intc 9>,
> +					      <&cpu2_intc 11>,
> <&cpu2_intc 9>,
> +					      <&cpu3_intc 11>,
> <&cpu3_intc 9>,
> +					      <&cpu4_intc 11>,
> <&cpu4_intc 9>;
> +			riscv,ndev = <186>;
> +		};
> +
> +		pdma: dma-controller@3000000 {
> +			compatible = "sifive,fu540-c000-pdma",
> "sifive,pdma0";
> +			reg = <0x0 0x3000000 0x0 0x8000>;
> +			interrupt-parent = <&plic>;
> +			interrupts = <5 6>, <7 8>, <9 10>, <11 12>;
> +			dma-channels = <4>;
> +			#dma-cells = <1>;
>  		};
>  
>  		clkcfg: clkcfg@20002000 {
>  			compatible = "microchip,mpfs-clkcfg";
>  			reg = <0x0 0x20002000 0x0 0x1000>, <0x0
> 0x3E001000 0x0 0x1000>;
> -			reg-names = "mss_sysreg";
>  			clocks = <&refclk>;
>  			#clock-cells = <1>;
> -			clock-output-names = "cpu", "axi", "ahb",
> "envm",	/* 0-3   */
> -				"mac0", "mac1", "mmc", "timer",		
> 		/* 4-7   */
> -				"mmuart0", "mmuart1", "mmuart2",
> "mmuart3",	/* 8-11  */
> -				"mmuart4", "spi0", "spi1", "i2c0",	
> 		/* 12-15 */
> -				"i2c1", "can0", "can1", "usb",		
> 		/* 16-19 */
> -				"rsvd", "rtc", "qspi", "gpio0",		
> 		/* 20-23 */
> -				"gpio1", "gpio2", "ddrc", "fic0",		
> 	/* 24-27 */
> -				"fic1", "fic2", "fic3", "athena",
> "cfm";	/* 28-32 */
> +			#reset-cells = <1>;
>  		};
>  
> -		/* Common node entry for eMMC/SD */
> -		mmc: mmc@20008000 {
> -			compatible = "microchip,mpfs-
> sd4hc","cdns,sd4hc";
> -			reg = <0x0 0x20008000 0x0 0x1000>;
> -			clocks = <&clkcfg CLK_MMC>;
> -			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_MMC_MAIN
> PLIC_INT_MMC_WAKEUP>;
> -			max-frequency = <200000000>;
> +		ccc_se: clock-controller@38010000 {
> +			compatible = "microchip,mpfs-ccc";
> +			reg = <0x0 0x38010000 0x0 0x1000>, <0x0
> 0x38020000 0x0 0x1000>,
> +			      <0x0 0x39010000 0x0 0x1000>, <0x0
> 0x39020000 0x0 0x1000>;
> +			#clock-cells = <1>;
>  			status = "disabled";
>  		};
>  
> -		uart0: serial@20000000 {
> +		ccc_ne: clock-controller@38040000 {
> +			compatible = "microchip,mpfs-ccc";
> +			reg = <0x0 0x38040000 0x0 0x1000>, <0x0
> 0x38080000 0x0 0x1000>,
> +			      <0x0 0x39040000 0x0 0x1000>, <0x0
> 0x39080000 0x0 0x1000>;
> +			#clock-cells = <1>;
> +			status = "disabled";
> +		};
> +
> +		ccc_nw: clock-controller@38100000 {
> +			compatible = "microchip,mpfs-ccc";
> +			reg = <0x0 0x38100000 0x0 0x1000>, <0x0
> 0x38200000 0x0 0x1000>,
> +			      <0x0 0x39100000 0x0 0x1000>, <0x0
> 0x39200000 0x0 0x1000>;
> +			#clock-cells = <1>;
> +			status = "disabled";
> +		};
> +
> +		ccc_sw: clock-controller@38400000 {
> +			compatible = "microchip,mpfs-ccc";
> +			reg = <0x0 0x38400000 0x0 0x1000>, <0x0
> 0x38800000 0x0 0x1000>,
> +			      <0x0 0x39400000 0x0 0x1000>, <0x0
> 0x39800000 0x0 0x1000>;
> +			#clock-cells = <1>;
> +			status = "disabled";
> +		};
> +
> +		mmuart0: serial@20000000 {
>  			compatible = "ns16550a";
>  			reg = <0x0 0x20000000 0x0 0x400>;
>  			reg-io-width = <4>;
>  			reg-shift = <2>;
>  			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_MMUART0>;
> +			interrupts = <90>;
> +			current-speed = <115200>;
>  			clocks = <&clkcfg CLK_MMUART0>;
>  			status = "disabled"; /* Reserved for the HSS */
>  		};
>  
> -		uart1: serial@20100000 {
> +		mmuart1: serial@20100000 {
>  			compatible = "ns16550a";
>  			reg = <0x0 0x20100000 0x0 0x400>;
>  			reg-io-width = <4>;
>  			reg-shift = <2>;
>  			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_MMUART1>;
> +			interrupts = <91>;
> +			current-speed = <115200>;
>  			clocks = <&clkcfg CLK_MMUART1>;
>  			status = "disabled";
>  		};
>  
> -		uart2: serial@20102000 {
> +		mmuart2: serial@20102000 {
>  			compatible = "ns16550a";
>  			reg = <0x0 0x20102000 0x0 0x400>;
>  			reg-io-width = <4>;
>  			reg-shift = <2>;
>  			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_MMUART2>;
> +			interrupts = <92>;
> +			current-speed = <115200>;
>  			clocks = <&clkcfg CLK_MMUART2>;
>  			status = "disabled";
>  		};
>  
> -		uart3: serial@20104000 {
> +		mmuart3: serial@20104000 {
>  			compatible = "ns16550a";
>  			reg = <0x0 0x20104000 0x0 0x400>;
>  			reg-io-width = <4>;
>  			reg-shift = <2>;
>  			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_MMUART3>;
> +			interrupts = <93>;
> +			current-speed = <115200>;
>  			clocks = <&clkcfg CLK_MMUART3>;
>  			status = "disabled";
>  		};
>  
> -		uart4: serial@20106000 {
> +		mmuart4: serial@20106000 {
>  			compatible = "ns16550a";
>  			reg = <0x0 0x20106000 0x0 0x400>;
>  			reg-io-width = <4>;
>  			reg-shift = <2>;
>  			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_MMUART4>;
> +			interrupts = <94>;
>  			clocks = <&clkcfg CLK_MMUART4>;
> +			current-speed = <115200>;
> +			status = "disabled";
> +		};
> +
> +		/* Common node entry for emmc/sd */
> +		mmc: mmc@20008000 {
> +			compatible = "microchip,mpfs-sd4hc",
> "cdns,sd4hc";
> +			reg = <0x0 0x20008000 0x0 0x1000>;
> +			interrupt-parent = <&plic>;
> +			interrupts = <88>;
> +			clocks = <&clkcfg CLK_MMC>;
> +			max-frequency = <200000000>;
>  			status = "disabled";
>  		};
>  
>  		spi0: spi@20108000 {
>  			compatible = "microchip,mpfs-spi";
> -			reg = <0x0 0x20108000 0x0 0x1000>;
> -			clocks = <&clkcfg CLK_SPI0>;
> -			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_SPI0>;
> -			num-cs = <8>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> +			reg = <0x0 0x20108000 0x0 0x1000>;
> +			interrupt-parent = <&plic>;
> +			interrupts = <54>;
> +			clocks = <&clkcfg CLK_SPI0>;
>  			status = "disabled";
>  		};
>  
>  		spi1: spi@20109000 {
>  			compatible = "microchip,mpfs-spi";
> -			reg = <0x0 0x20109000 0x0 0x1000>;
> -			clocks = <&clkcfg CLK_SPI1>;
> -			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_SPI1>;
> -			num-cs = <8>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> +			reg = <0x0 0x20109000 0x0 0x1000>;
> +			interrupt-parent = <&plic>;
> +			interrupts = <55>;
> +			clocks = <&clkcfg CLK_SPI1>;
> +			status = "disabled";
> +		};
> +
> +		qspi: spi@21000000 {
> +			compatible = "microchip,mpfs-qspi",
> "microchip,coreqspi-rtl-v2";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x0 0x21000000 0x0 0x1000>;
> +			interrupt-parent = <&plic>;
> +			interrupts = <85>;
> +			clocks = <&clkcfg CLK_QSPI>;
>  			status = "disabled";
>  		};
>  
>  		i2c0: i2c@2010a000 {
> -			compatible = "microchip,mpfs-i2c";
> +			compatible = "microchip,mpfs-i2c",
> "microchip,corei2c-rtl-v7";
>  			reg = <0x0 0x2010a000 0x0 0x1000>;
> -			clocks = <&clkcfg CLK_I2C0>;
> -			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_I2C0_MAIN>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> +			interrupt-parent = <&plic>;
> +			interrupts = <58>;
> +			clocks = <&clkcfg CLK_I2C0>;
> +			clock-frequency = <100000>;
>  			status = "disabled";
>  		};
>  
>  		i2c1: i2c@2010b000 {
> -			compatible = "microchip,mpfs-i2c";
> +			compatible = "microchip,mpfs-i2c",
> "microchip,corei2c-rtl-v7";
>  			reg = <0x0 0x2010b000 0x0 0x1000>;
> -			clocks = <&clkcfg CLK_I2C1>;
> -			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_I2C1_MAIN>;
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> +			interrupt-parent = <&plic>;
> +			interrupts = <61>;
> +			clocks = <&clkcfg CLK_I2C1>;
> +			clock-frequency = <100000>;
>  			status = "disabled";
>  		};
>  
>  		can0: can@2010c000 {
> -			compatible = "microchip,mpfs-can-uio";
> +			compatible = "microchip,mpfs-can";
>  			reg = <0x0 0x2010c000 0x0 0x1000>;
>  			clocks = <&clkcfg CLK_CAN0>;
>  			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_CAN0>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> +			interrupts = <56>;
>  			status = "disabled";
>  		};
>  
>  		can1: can@2010d000 {
> -			compatible = "microchip,mpfs-can-uio";
> +			compatible = "microchip,mpfs-can";
>  			reg = <0x0 0x2010d000 0x0 0x1000>;
>  			clocks = <&clkcfg CLK_CAN1>;
>  			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_CAN1>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> +			interrupts = <57>;
>  			status = "disabled";
>  		};
>  
>  		mac0: ethernet@20110000 {
> -			compatible = "cdns,macb";
> +			compatible = "microchip,mpfs-macb",
> "cdns,macb";
>  			reg = <0x0 0x20110000 0x0 0x2000>;
> -			clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
> -			clock-names = "pclk", "hclk";
> -			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_MAC0_INT
> -				PLIC_INT_MAC0_QUEUE1
> -				PLIC_INT_MAC0_QUEUE2
> -				PLIC_INT_MAC0_QUEUE3
> -				PLIC_INT_MAC0_EMAC
> -				PLIC_INT_MAC0_MMSL>;
> -			local-mac-address = [00 00 00 00 00 00];
> -			status = "disabled";
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> +			interrupt-parent = <&plic>;
> +			interrupts = <64>, <65>, <66>, <67>, <68>,
> <69>;
> +			local-mac-address = [00 00 00 00 00 00];
> +			clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
> +			clock-names = "pclk", "hclk";
> +			resets = <&clkcfg CLK_MAC0>;
> +			status = "disabled";
>  		};
>  
>  		mac1: ethernet@20112000 {
> -			compatible = "cdns,macb";
> +			compatible = "microchip,mpfs-macb",
> "cdns,macb";
>  			reg = <0x0 0x20112000 0x0 0x2000>;
> -			clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
> -			clock-names = "pclk", "hclk";
> -			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_MAC1_INT
> -				PLIC_INT_MAC1_QUEUE1
> -				PLIC_INT_MAC1_QUEUE2
> -				PLIC_INT_MAC1_QUEUE3
> -				PLIC_INT_MAC1_EMAC
> -				PLIC_INT_MAC1_MMSL>;
> -			local-mac-address = [00 00 00 00 00 00];
> -			status = "disabled";
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> +			interrupt-parent = <&plic>;
> +			interrupts = <70>, <71>, <72>, <73>, <74>,
> <75>;
> +			local-mac-address = [00 00 00 00 00 00];
> +			clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
> +			clock-names = "pclk", "hclk";
> +			resets = <&clkcfg CLK_MAC1>;
> +			status = "disabled";
>  		};
>  
>  		gpio0: gpio@20120000 {
>  			compatible = "microchip,mpfs-gpio";
>  			reg = <0x0 0x20120000 0x0 0x1000>;
> -			reg-names = "control";
> -			clocks = <&clkcfg CLK_GPIO0>;
>  			interrupt-parent = <&plic>;
> +			interrupt-controller;
> +			#interrupt-cells = <1>;
> +			clocks = <&clkcfg CLK_GPIO0>;
>  			gpio-controller;
>  			#gpio-cells = <2>;
>  			status = "disabled";
> @@ -429,10 +456,11 @@
>  
>  		gpio1: gpio@20121000 {
>  			compatible = "microchip,mpfs-gpio";
> -			reg = <000 0x20121000 0x0 0x1000>;
> -			reg-names = "control";
> -			clocks = <&clkcfg CLK_GPIO1>;
> +			reg = <0x0 0x20121000 0x0 0x1000>;
>  			interrupt-parent = <&plic>;
> +			interrupt-controller;
> +			#interrupt-cells = <1>;
> +			clocks = <&clkcfg CLK_GPIO1>;
>  			gpio-controller;
>  			#gpio-cells = <2>;
>  			status = "disabled";
> @@ -441,9 +469,10 @@
>  		gpio2: gpio@20122000 {
>  			compatible = "microchip,mpfs-gpio";
>  			reg = <0x0 0x20122000 0x0 0x1000>;
> -			reg-names = "control";
> -			clocks = <&clkcfg CLK_GPIO2>;
>  			interrupt-parent = <&plic>;
> +			interrupt-controller;
> +			#interrupt-cells = <1>;
> +			clocks = <&clkcfg CLK_GPIO2>;
>  			gpio-controller;
>  			#gpio-cells = <2>;
>  			status = "disabled";
> @@ -452,118 +481,31 @@
>  		rtc: rtc@20124000 {
>  			compatible = "microchip,mpfs-rtc";
>  			reg = <0x0 0x20124000 0x0 0x1000>;
> -			clocks = <&clkcfg CLK_RTC>;
> -			clock-names = "rtc";
>  			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_RTC_WAKEUP
> PLIC_INT_RTC_MATCH>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
> +			interrupts = <80>, <81>;
> +			clocks = <&clkcfg CLK_RTC>, <&clkcfg
> CLK_RTCREF>;
> +			clock-names = "rtc", "rtcref";
>  			status = "disabled";
>  		};
>  
>  		usb: usb@20201000 {
> -			compatible = "microchip,mpfs-usb-host";
> +			compatible = "microchip,mpfs-musb";
>  			reg = <0x0 0x20201000 0x0 0x1000>;
> -			reg-names = "mc","control";
> +			interrupt-parent = <&plic>;
> +			interrupts = <86>, <87>;
>  			clocks = <&clkcfg CLK_USB>;
> -			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_USB_DMA
> PLIC_INT_USB_MC>;
>  			interrupt-names = "dma","mc";
> -			dr_mode = "host";
> -			status = "disabled";
> -		};
> -
> -		qspi: qspi@21000000 {
> -			compatible = "microchip,mpfs-qspi";
> -			reg = <0x0 0x21000000 0x0 0x1000>;
> -			clocks = <&clkcfg CLK_QSPI>;
> -			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_QSPI>;
> -			num-cs = <8>;
> -			#address-cells = <1>;
> -			#size-cells = <0>;
>  			status = "disabled";
>  		};
>  
>  		mbox: mailbox@37020000 {
>  			compatible = "microchip,mpfs-mailbox";
> -			reg = <0x0 0x37020000 0x0 0x1000>, <0x0
> 0x2000318C 0x0 0x40>;
> +			reg = <0x0 0x37020000 0x0 0x58>, <0x0
> 0x2000318C 0x0 0x40>,
> +			      <0x0 0x37020800 0x0 0x100>;
>  			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_G5C_MESSAGE>;
> +			interrupts = <96>;
>  			#mbox-cells = <1>;
>  			status = "disabled";
>  		};
> -
> -		pcie: pcie@2000000000 {
> -			compatible = "microchip,pcie-host-1.0";
> -			#address-cells = <0x3>;
> -			#interrupt-cells = <0x1>;
> -			#size-cells = <0x2>;
> -			device_type = "pci";
> -			reg = <0x20 0x0 0x0 0x8000000 0x0 0x43000000
> 0x0 0x10000>;
> -			reg-names = "cfg", "apb";
> -			clocks = <&clkcfg CLK_FIC0>, <&clkcfg
> CLK_FIC1>, <&clkcfg CLK_FIC3>;
> -			clock-names = "fic0", "fic1", "fic3";
> -			bus-range = <0x0 0x7f>;
> -			interrupt-parent = <&plic>;
> -			interrupts = <PLIC_INT_FABRIC_F2H_2>;
> -			interrupt-map = <0 0 0 1 &pcie_intc 0>,
> -					<0 0 0 2 &pcie_intc 1>,
> -					<0 0 0 3 &pcie_intc 2>,
> -					<0 0 0 4 &pcie_intc 3>;
> -			interrupt-map-mask = <0 0 0 7>;
> -			ranges = <0x3000000 0x0 0x8000000 0x20
> 0x8000000 0x0 0x80000000>;
> -			msi-parent = <&pcie>;
> -			msi-controller;
> -			mchp,axi-m-atr0 = <0x10 0x0>;
> -			status = "disabled";
> -			pcie_intc: legacy-interrupt-controller {
> -				#address-cells = <0>;
> -				#interrupt-cells = <1>;
> -				interrupt-controller;
> -			};
> -		};
> -
> -		syscontroller: syscontroller {
> -			compatible = "microchip,mpfs-sys-controller";
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			mboxes = <&mbox 0>;
> -		};
> -
> -		hwrandom: hwrandom {
> -			compatible = "microchip,mpfs-rng";
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			syscontroller = <&syscontroller>;
> -		};
> -
> -		serialnum: serialnum {
> -			compatible = "microchip,mpfs-serial-number";
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			syscontroller = <&syscontroller>;
> -		};
> -
> -		fpgadigest: fpgadigest {
> -			compatible = "microchip,mpfs-digest";
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			syscontroller = <&syscontroller>;
> -		};
> -
> -		devicecert: cert {
> -			compatible = "microchip,mpfs-device-cert";
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			syscontroller = <&syscontroller>;
> -		};
> -
> -		signature: signature {
> -			compatible = "microchip,mpfs-signature";
> -			#address-cells = <1>;
> -			#size-cells = <1>;
> -			syscontroller = <&syscontroller>;
> -		};
>  	};
>  };
> diff --git a/include/dt-bindings/clock/microchip-mpfs-clock.h
> b/include/dt-bindings/clock/microchip-mpfs-clock.h
> index c7ed0a8db7..79775a5134 100644
> --- a/include/dt-bindings/clock/microchip-mpfs-clock.h
> +++ b/include/dt-bindings/clock/microchip-mpfs-clock.h
> @@ -1,7 +1,7 @@
> -/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
>  /*
> - * Copyright (C) 2020 Microchip Technology Inc.
> - * Padmarao Begari <padmarao.begari@microchip.com>
> + * Daire McNamara,<daire.mcnamara@microchip.com>
> + * Copyright (C) 2020-2022 Microchip Technology Inc.  All rights
> reserved.
>   */
>  
>  #ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
> @@ -45,4 +45,27 @@
>  #define CLK_RTCREF	33
>  #define CLK_MSSPLL	34
>  
> +/* Clock Conditioning Circuitry Clock IDs */
> +
> +#define CLK_CCC_PLL0		0
> +#define CLK_CCC_PLL1		1
> +#define CLK_CCC_DLL0		2
> +#define CLK_CCC_DLL1		3
> +
> +#define CLK_CCC_PLL0_OUT0	4
> +#define CLK_CCC_PLL0_OUT1	5
> +#define CLK_CCC_PLL0_OUT2	6
> +#define CLK_CCC_PLL0_OUT3	7
> +
> +#define CLK_CCC_PLL1_OUT0	8
> +#define CLK_CCC_PLL1_OUT1	9
> +#define CLK_CCC_PLL1_OUT2	10
> +#define CLK_CCC_PLL1_OUT3	11
> +
> +#define CLK_CCC_DLL0_OUT0	12
> +#define CLK_CCC_DLL0_OUT1	13
> +
> +#define CLK_CCC_DLL1_OUT0	14
> +#define CLK_CCC_DLL1_OUT1	15
> +
>  #endif	/* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */
> diff --git a/include/dt-bindings/interrupt-controller/microchip-mpfs-
> plic.h b/include/dt-bindings/interrupt-controller/microchip-mpfs-
> plic.h
> deleted file mode 100644
> index eba1bac7df..0000000000
> --- a/include/dt-bindings/interrupt-controller/microchip-mpfs-plic.h
> +++ /dev/null
> @@ -1,196 +0,0 @@
> -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> -/* Copyright (c) 2020-2021 Microchip Technology Inc */
> -
> -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H
> -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H
> -
> -#define PLIC_INT_INVALID						
> 0
> -#define PLIC_INT_L2_METADATA_CORR				1
> -#define PLIC_INT_L2_METADATA_UNCORR				2
> -#define PLIC_INT_L2_DATA_CORR					
> 3
> -#define PLIC_INT_L2_DATA_UNCORR					
> 4
> -#define PLIC_INT_DMA_CH0_DONE					
> 5
> -#define PLIC_INT_DMA_CH0_ERR					6
> -#define PLIC_INT_DMA_CH1_DONE					
> 7
> -#define PLIC_INT_DMA_CH1_ERR					8
> -#define PLIC_INT_DMA_CH2_DONE					
> 9
> -#define PLIC_INT_DMA_CH2_ERR					10
> -#define PLIC_INT_DMA_CH3_DONE					
> 11
> -#define PLIC_INT_DMA_CH3_ERR					12
> -
> -#define PLIC_INT_GPIO0_BIT0_OR_GPIO2_BIT0		13
> -#define PLIC_INT_GPIO0_BIT1_OR_GPIO2_BIT1		14
> -#define PLIC_INT_GPIO0_BIT2_OR_GPIO2_BIT2		15
> -#define PLIC_INT_GPIO0_BIT3_OR_GPIO2_BIT3		16
> -#define PLIC_INT_GPIO0_BIT4_OR_GPIO2_BIT4		17
> -#define PLIC_INT_GPIO0_BIT5_OR_GPIO2_BIT5		18
> -#define PLIC_INT_GPIO0_BIT6_OR_GPIO2_BIT6		19
> -#define PLIC_INT_GPIO0_BIT7_OR_GPIO2_BIT7		20
> -#define PLIC_INT_GPIO0_BIT8_OR_GPIO2_BIT8		21
> -#define PLIC_INT_GPIO0_BIT9_OR_GPIO2_BIT9		22
> -#define PLIC_INT_GPIO0_BIT10_OR_GPIO2_BIT10		23
> -#define PLIC_INT_GPIO0_BIT11_OR_GPIO2_BIT11		24
> -#define PLIC_INT_GPIO0_BIT12_OR_GPIO2_BIT12		25
> -#define PLIC_INT_GPIO0_BIT13_OR_GPIO2_BIT13		26
> -#define PLIC_INT_GPIO1_BIT0_OR_GPIO2_BIT14		27
> -#define PLIC_INT_GPIO1_BIT1_OR_GPIO2_BIT15		28
> -#define PLIC_INT_GPIO1_BIT2_OR_GPIO2_BIT16		29
> -#define PLIC_INT_GPIO1_BIT3_OR_GPIO2_BIT17		30
> -#define PLIC_INT_GPIO1_BIT4_OR_GPIO2_BIT18		31
> -#define PLIC_INT_GPIO1_BIT5_OR_GPIO2_BIT19		32
> -#define PLIC_INT_GPIO1_BIT6_OR_GPIO2_BIT20		33
> -#define PLIC_INT_GPIO1_BIT7_OR_GPIO2_BIT21		34
> -#define PLIC_INT_GPIO1_BIT8_OR_GPIO2_BIT22		35
> -#define PLIC_INT_GPIO1_BIT9_OR_GPIO2_BIT23		36
> -#define PLIC_INT_GPIO1_BIT10_OR_GPIO2_BIT24		37
> -#define PLIC_INT_GPIO1_BIT11_OR_GPIO2_BIT25		38
> -#define PLIC_INT_GPIO1_BIT12_OR_GPIO2_BIT26		39
> -#define PLIC_INT_GPIO1_BIT13_OR_GPIO2_BIT27		40
> -#define PLIC_INT_GPIO1_BIT14_OR_GPIO2_BIT28		41
> -#define PLIC_INT_GPIO1_BIT15_OR_GPIO2_BIT29		42
> -#define PLIC_INT_GPIO1_BIT16_OR_GPIO2_BIT30		43
> -#define PLIC_INT_GPIO1_BIT17_OR_GPIO2_BIT31		44
> -#define PLIC_INT_GPIO1_BIT18					45
> -#define PLIC_INT_GPIO1_BIT19					46
> -#define PLIC_INT_GPIO1_BIT20					47
> -#define PLIC_INT_GPIO1_BIT21					48
> -#define PLIC_INT_GPIO1_BIT22					49
> -#define PLIC_INT_GPIO1_BIT23					50
> -#define PLIC_INT_GPIO0_NON_DIRECT				51
> -#define PLIC_INT_GPIO1_NON_DIRECT				52
> -#define PLIC_INT_GPIO2_NON_DIRECT				53
> -#define PLIC_INT_SPI0						
> 	54
> -#define PLIC_INT_SPI1						
> 	55
> -#define PLIC_INT_CAN0						
> 	56
> -#define PLIC_INT_CAN1						
> 	57
> -#define PLIC_INT_I2C0_MAIN						
> 58
> -#define PLIC_INT_I2C0_ALERT						
> 59
> -#define PLIC_INT_I2C0_SUS						
> 60
> -#define PLIC_INT_I2C1_MAIN						
> 61
> -#define PLIC_INT_I2C1_ALERT						
> 62
> -#define PLIC_INT_I2C1_SUS						
> 63
> -#define PLIC_INT_MAC0_INT						
> 64
> -#define PLIC_INT_MAC0_QUEUE1					65
> -#define PLIC_INT_MAC0_QUEUE2					66
> -#define PLIC_INT_MAC0_QUEUE3					67
> -#define PLIC_INT_MAC0_EMAC						
> 68
> -#define PLIC_INT_MAC0_MMSL						
> 69
> -#define PLIC_INT_MAC1_INT						
> 70
> -#define PLIC_INT_MAC1_QUEUE1					71
> -#define PLIC_INT_MAC1_QUEUE2					72
> -#define PLIC_INT_MAC1_QUEUE3					73
> -#define PLIC_INT_MAC1_EMAC						
> 74
> -#define PLIC_INT_MAC1_MMSL						
> 75
> -#define PLIC_INT_DDRC_TRAIN						
> 76
> -#define PLIC_INT_SCB_INTERRUPT					
> 77
> -#define PLIC_INT_ECC_ERROR						
> 78
> -#define PLIC_INT_ECC_CORRECT					79
> -#define PLIC_INT_RTC_WAKEUP						
> 80
> -#define PLIC_INT_RTC_MATCH						
> 81
> -#define PLIC_INT_TIMER1						
> 	82
> -#define PLIC_INT_TIMER2						
> 	83
> -#define PLIC_INT_ENVM						
> 	84
> -#define PLIC_INT_QSPI						
> 	85
> -#define PLIC_INT_USB_DMA						
> 86
> -#define PLIC_INT_USB_MC						
> 	87
> -#define PLIC_INT_MMC_MAIN						
> 88
> -#define PLIC_INT_MMC_WAKEUP						
> 89
> -#define PLIC_INT_MMUART0						
> 90
> -#define PLIC_INT_MMUART1						
> 91
> -#define PLIC_INT_MMUART2						
> 92
> -#define PLIC_INT_MMUART3						
> 93
> -#define PLIC_INT_MMUART4						
> 94
> -#define PLIC_INT_G5C_DEVRST						
> 95
> -#define PLIC_INT_G5C_MESSAGE					96
> -#define PLIC_INT_USOC_VC_INTERRUPT				97
> -#define PLIC_INT_USOC_SMB_INTERRUPT				98
> -#define PLIC_INT_E51_0_MAINTENACE				99
> -#define PLIC_INT_WDOG0_MRVP						
> 100
> -#define PLIC_INT_WDOG1_MRVP						
> 101
> -#define PLIC_INT_WDOG2_MRVP						
> 102
> -#define PLIC_INT_WDOG3_MRVP						
> 103
> -#define PLIC_INT_WDOG4_MRVP						
> 104
> -#define PLIC_INT_WDOG0_TOUT						
> 105
> -#define PLIC_INT_WDOG1_TOUT						
> 106
> -#define PLIC_INT_WDOG2_TOUT						
> 107
> -#define PLIC_INT_WDOG3_TOUT						
> 108
> -#define PLIC_INT_WDOG4_TOUT						
> 109
> -#define PLIC_INT_G5C_MSS_SPI					110
> -#define PLIC_INT_VOLT_TEMP_ALARM				111
> -#define PLIC_INT_ATHENA_COMPLETE				112
> -#define PLIC_INT_ATHENA_ALARM					
> 113
> -#define PLIC_INT_ATHENA_BUS_ERROR				114
> -#define PLIC_INT_USOC_AXIC_US					
> 115
> -#define PLIC_INT_USOC_AXIC_DS					
> 116
> -#define PLIC_INT_SPARE						
> 	117
> -#define PLIC_INT_FABRIC_F2H_0					
> 118
> -#define PLIC_INT_FABRIC_F2H_1					
> 119
> -#define PLIC_INT_FABRIC_F2H_2					
> 120
> -#define PLIC_INT_FABRIC_F2H_3					
> 121
> -#define PLIC_INT_FABRIC_F2H_4					
> 122
> -#define PLIC_INT_FABRIC_F2H_5					
> 123
> -#define PLIC_INT_FABRIC_F2H_6					
> 124
> -#define PLIC_INT_FABRIC_F2H_7					
> 125
> -#define PLIC_INT_FABRIC_F2H_8					
> 126
> -#define PLIC_INT_FABRIC_F2H_9					
> 127
> -#define PLIC_INT_FABRIC_F2H_10					
> 128
> -#define PLIC_INT_FABRIC_F2H_11					
> 129
> -#define PLIC_INT_FABRIC_F2H_12					
> 130
> -#define PLIC_INT_FABRIC_F2H_13					
> 131
> -#define PLIC_INT_FABRIC_F2H_14					
> 132
> -#define PLIC_INT_FABRIC_F2H_15					
> 133
> -#define PLIC_INT_FABRIC_F2H_16					
> 134
> -#define PLIC_INT_FABRIC_F2H_17					
> 135
> -#define PLIC_INT_FABRIC_F2H_18					
> 136
> -#define PLIC_INT_FABRIC_F2H_19					
> 137
> -#define PLIC_INT_FABRIC_F2H_20					
> 138
> -#define PLIC_INT_FABRIC_F2H_21					
> 139
> -#define PLIC_INT_FABRIC_F2H_22					
> 140
> -#define PLIC_INT_FABRIC_F2H_23					
> 141
> -#define PLIC_INT_FABRIC_F2H_24					
> 142
> -#define PLIC_INT_FABRIC_F2H_25					
> 143
> -#define PLIC_INT_FABRIC_F2H_26					
> 144
> -#define PLIC_INT_FABRIC_F2H_27					
> 145
> -#define PLIC_INT_FABRIC_F2H_28					
> 146
> -#define PLIC_INT_FABRIC_F2H_29					
> 147
> -#define PLIC_INT_FABRIC_F2H_30					
> 148
> -#define PLIC_INT_FABRIC_F2H_31					
> 149
> -#define PLIC_INT_FABRIC_F2H_32					
> 150
> -#define PLIC_INT_FABRIC_F2H_33					
> 151
> -#define PLIC_INT_FABRIC_F2H_34					
> 152
> -#define PLIC_INT_FABRIC_F2H_35					
> 153
> -#define PLIC_INT_FABRIC_F2H_36					
> 154
> -#define PLIC_INT_FABRIC_F2H_37					
> 155
> -#define PLIC_INT_FABRIC_F2H_38					
> 156
> -#define PLIC_INT_FABRIC_F2H_39					
> 157
> -#define PLIC_INT_FABRIC_F2H_40					
> 158
> -#define PLIC_INT_FABRIC_F2H_41					
> 159
> -#define PLIC_INT_FABRIC_F2H_42					
> 160
> -#define PLIC_INT_FABRIC_F2H_43					
> 161
> -#define PLIC_INT_FABRIC_F2H_44					
> 162
> -#define PLIC_INT_FABRIC_F2H_45					
> 163
> -#define PLIC_INT_FABRIC_F2H_46					
> 164
> -#define PLIC_INT_FABRIC_F2H_47					
> 165
> -#define PLIC_INT_FABRIC_F2H_48					
> 166
> -#define PLIC_INT_FABRIC_F2H_49					
> 167
> -#define PLIC_INT_FABRIC_F2H_50					
> 168
> -#define PLIC_INT_FABRIC_F2H_51					
> 169
> -#define PLIC_INT_FABRIC_F2H_52					
> 170
> -#define PLIC_INT_FABRIC_F2H_53					
> 171
> -#define PLIC_INT_FABRIC_F2H_54					
> 172
> -#define PLIC_INT_FABRIC_F2H_55					
> 173
> -#define PLIC_INT_FABRIC_F2H_56					
> 174
> -#define PLIC_INT_FABRIC_F2H_57					
> 175
> -#define PLIC_INT_FABRIC_F2H_58					
> 176
> -#define PLIC_INT_FABRIC_F2H_59					
> 177
> -#define PLIC_INT_FABRIC_F2H_60					
> 178
> -#define PLIC_INT_FABRIC_F2H_61					
> 179
> -#define PLIC_INT_FABRIC_F2H_62					
> 180
> -#define PLIC_INT_FABRIC_F2H_63					
> 181
> -#define PLIC_INT_BUS_ERROR_UNIT_HART_0			182
> -#define PLIC_INT_BUS_ERROR_UNIT_HART_1			183
> -#define PLIC_INT_BUS_ERROR_UNIT_HART_2			184
> -#define PLIC_INT_BUS_ERROR_UNIT_HART_3			185
> -#define PLIC_INT_BUS_ERROR_UNIT_HART_4			186
> -
> -#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_MICROCHIP_MPFS_PLIC_H */
> diff --git a/include/dt-bindings/interrupt-controller/riscv-hart.h
> b/include/dt-bindings/interrupt-controller/riscv-hart.h
> deleted file mode 100644
> index c4331b8521..0000000000
> --- a/include/dt-bindings/interrupt-controller/riscv-hart.h
> +++ /dev/null
> @@ -1,17 +0,0 @@
> -/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> -/* Copyright (c) 2020-2021 Microchip Technology Inc */
> -
> -#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
> -#define _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H
> -
> -#define HART_INT_U_SOFT   0
> -#define HART_INT_S_SOFT   1
> -#define HART_INT_M_SOFT   3
> -#define HART_INT_U_TIMER  4
> -#define HART_INT_S_TIMER  5
> -#define HART_INT_M_TIMER  7
> -#define HART_INT_U_EXT    8
> -#define HART_INT_S_EXT    9
> -#define HART_INT_M_EXT    11
> -
> -#endif /* _DT_BINDINGS_INTERRUPT_CONTROLLER_RISCV_HART_H */