diff mbox series

[v2,3/3] riscv: dts: starfive: Enable PCIe host controller

Message ID 20230308054833.95730-4-minda.chen@starfivetech.com
State Superseded
Delegated to: Andes
Headers show
Series Add StarFive JH7110 PCIe drvier support | expand

Commit Message

Minda Chen March 8, 2023, 5:48 a.m. UTC 
From: Mason Huo <mason.huo@starfivetech.com>

Enable and add pinctrl configuration for PCIe host controller.
Also add JH7110 stg syscon configuration.

Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
 .../dts/jh7110-starfive-visionfive-2.dtsi     | 99 +++++++++++++++++++
 arch/riscv/dts/jh7110.dtsi                    | 75 ++++++++++++++
 2 files changed, 174 insertions(+)

Comments

Pali Rohár March 25, 2023, 1:22 p.m. UTC | #1 
On Wednesday 08 March 2023 13:48:33 Minda Chen wrote:
> From: Mason Huo <mason.huo@starfivetech.com>
> 
> Enable and add pinctrl configuration for PCIe host controller.
> Also add JH7110 stg syscon configuration.
> 
> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> ---
>  .../dts/jh7110-starfive-visionfive-2.dtsi     | 99 +++++++++++++++++++
>  arch/riscv/dts/jh7110.dtsi                    | 75 ++++++++++++++
>  2 files changed, 174 insertions(+)
> 
> diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> index e669c2a26a..995f842a6b 100644
> --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
> @@ -178,6 +178,87 @@
>  			slew-rate = <0>;
>  		};
>  	};
> +
> +	pcie0_perst_default: pcie0_perst_default {
> +		perst-pins {
> +			pinmux = <GPIOMUX(26, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
> +			drive-strength = <2>;
> +			input-disable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;
> +		};
> +	};
> +
> +	pcie0_perst_active: pcie0_perst_active {
> +		perst-pins {
> +			pinmux = <GPIOMUX(26, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
> +			drive-strength = <2>;
> +			input-disable;
> +			input-schmitt-disable;
> +			slew-rate = <0>;
> +		};
> +	};
...
> +&pcie0 {
> +	pinctrl-names = "perst-default", "perst-active", "wake-default", "clkreq-default";
> +	pinctrl-0 = <&pcie0_perst_default>;
> +	pinctrl-1 = <&pcie0_perst_active>;
> +	pinctrl-2 = <&pcie0_wake_default>;
> +	pinctrl-3 = <&pcie0_clkreq_default>;
> +	status = "disabled";
> +};

This is not correct declaration of PERST# signal. You should define in
&pcie0 node "reset-gpios" property with plain gpio definition with
active state.

"reset-gpios" is standard PCIe property for controlling PERST# signal
over GPIO. Look for example into drivers/pci/pci-aardvark.c and
arch/arm/dts/armada-3720-espressobin.dtsi files how it is used.
Minda Chen March 27, 2023, 1:04 a.m. UTC | #2 
On 2023/3/25 21:22, Pali Rohár wrote:
> On Wednesday 08 March 2023 13:48:33 Minda Chen wrote:
>> From: Mason Huo <mason.huo@starfivetech.com>
>> 
>> Enable and add pinctrl configuration for PCIe host controller.
>> Also add JH7110 stg syscon configuration.
>> 
>> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
>> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
>> ---
>>  .../dts/jh7110-starfive-visionfive-2.dtsi     | 99 +++++++++++++++++++
>>  arch/riscv/dts/jh7110.dtsi                    | 75 ++++++++++++++
>>  2 files changed, 174 insertions(+)
>> 
>> diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
>> index e669c2a26a..995f842a6b 100644
>> --- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
>> +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
>> @@ -178,6 +178,87 @@
>>  			slew-rate = <0>;
>>  		};
>>  	};
>> +
>> +	pcie0_perst_default: pcie0_perst_default {
>> +		perst-pins {
>> +			pinmux = <GPIOMUX(26, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
>> +			drive-strength = <2>;
>> +			input-disable;
>> +			input-schmitt-disable;
>> +			slew-rate = <0>;
>> +		};
>> +	};
>> +
>> +	pcie0_perst_active: pcie0_perst_active {
>> +		perst-pins {
>> +			pinmux = <GPIOMUX(26, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
>> +			drive-strength = <2>;
>> +			input-disable;
>> +			input-schmitt-disable;
>> +			slew-rate = <0>;
>> +		};
>> +	};
> ...
>> +&pcie0 {
>> +	pinctrl-names = "perst-default", "perst-active", "wake-default", "clkreq-default";
>> +	pinctrl-0 = <&pcie0_perst_default>;
>> +	pinctrl-1 = <&pcie0_perst_active>;
>> +	pinctrl-2 = <&pcie0_wake_default>;
>> +	pinctrl-3 = <&pcie0_clkreq_default>;
>> +	status = "disabled";
>> +};
> 
> This is not correct declaration of PERST# signal. You should define in
> &pcie0 node "reset-gpios" property with plain gpio definition with
> active state.
> 
> "reset-gpios" is standard PCIe property for controlling PERST# signal
> over GPIO. Look for example into drivers/pci/pci-aardvark.c and
> arch/arm/dts/armada-3720-espressobin.dtsi files how it is used.

OK, I will change this, thanks
diff mbox series

Patch

diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
index e669c2a26a..995f842a6b 100644
--- a/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/dts/jh7110-starfive-visionfive-2.dtsi
@@ -178,6 +178,87 @@ 
 			slew-rate = <0>;
 		};
 	};
+
+	pcie0_perst_default: pcie0_perst_default {
+		perst-pins {
+			pinmux = <GPIOMUX(26, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+			drive-strength = <2>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	pcie0_perst_active: pcie0_perst_active {
+		perst-pins {
+			pinmux = <GPIOMUX(26, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
+			drive-strength = <2>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	pcie0_wake_default: pcie0_wake_default {
+		wake-pins {
+			pinmux = <GPIOMUX(32, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+			drive-strength = <2>;
+			input-enable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	pcie0_clkreq_default: pcie0_clkreq_default {
+		clkreq-pins {
+			pinmux = <GPIOMUX(27, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+			drive-strength = <2>;
+			input-enable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	pcie1_perst_default: pcie1_perst_default {
+		perst-pins {
+			pinmux = <GPIOMUX(28, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+			drive-strength = <2>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	pcie1_perst_active: pcie1_perst_active {
+		perst-pins {
+			pinmux = <GPIOMUX(28, GPOUT_LOW, GPOEN_ENABLE, GPI_NONE)>;
+			drive-strength = <2>;
+			input-disable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	pcie1_wake_default: pcie1_wake_default {
+		wake-pins {
+			pinmux = <GPIOMUX(21, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+			drive-strength = <2>;
+			input-enable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
+	pcie1_clkreq_default: pcie1_clkreq_default {
+		clkreq-pins {
+			pinmux = <GPIOMUX(29, GPOUT_HIGH, GPOEN_ENABLE, GPI_NONE)>;
+			drive-strength = <2>;
+			input-enable;
+			input-schmitt-disable;
+			slew-rate = <0>;
+		};
+	};
+
 };
 
 &mmc0 {
@@ -234,6 +315,24 @@ 
 	};
 };
 
+&pcie0 {
+	pinctrl-names = "perst-default", "perst-active", "wake-default", "clkreq-default";
+	pinctrl-0 = <&pcie0_perst_default>;
+	pinctrl-1 = <&pcie0_perst_active>;
+	pinctrl-2 = <&pcie0_wake_default>;
+	pinctrl-3 = <&pcie0_clkreq_default>;
+	status = "disabled";
+};
+
+&pcie1 {
+	pinctrl-names = "perst-default", "perst-active", "wake-default", "clkreq-default";
+	pinctrl-0 = <&pcie1_perst_default>;
+	pinctrl-1 = <&pcie1_perst_active>;
+	pinctrl-2 = <&pcie1_wake_default>;
+	pinctrl-3 = <&pcie1_clkreq_default>;
+	status = "okay";
+};
+
 &syscrg {
 	assigned-clocks = <&syscrg JH7110_SYSCLK_CPU_ROOT>,
 			  <&syscrg JH7110_SYSCLK_BUS_ROOT>,
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index d3e9f92987..e43296c9d5 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -578,5 +578,80 @@ 
 			gpio-controller;
 			#gpio-cells = <2>;
 		};
+
+		pcie0: pcie@2B000000 {
+			compatible = "starfive,jh7110-pcie";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			reg = <0x0 0x2B000000 0x0 0x1000000>,
+			      <0x9 0x40000000 0x0 0x10000000>;
+			reg-names = "reg", "config";
+			device_type = "pci";
+			starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
+				<0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
+			msi-parent = <&plic>;
+			interrupts = <56>;
+			interrupt-controller;
+			interrupt-names = "msi";
+			interrupt-parent = <&plic>;
+			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+			interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+					<0x0 0x0 0x0 0x2 &plic 0x2>,
+					<0x0 0x0 0x0 0x3 &plic 0x3>,
+					<0x0 0x0 0x0 0x4 &plic 0x4>;
+			resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>,
+				 <&stgcrg JH7110_STGRST_PCIE0_SLV0>,
+				 <&stgcrg JH7110_STGRST_PCIE0_SLV>,
+				 <&stgcrg JH7110_STGRST_PCIE0_BRG>,
+				 <&stgcrg JH7110_STGRST_PCIE0_CORE>,
+				 <&stgcrg JH7110_STGRST_PCIE0_APB>;
+			clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+				 <&stgcrg JH7110_STGCLK_PCIE0_TL>,
+				 <&stgcrg JH7110_STGCLK_PCIE0_AXI>,
+				 <&stgcrg JH7110_STGCLK_PCIE0_APB>;
+			clock-names = "noc_bus_stg_axi", "pcie0_tl", "pcie0_axi", "pcie0_apb";
+			status = "disabled";
+		};
+
+		pcie1: pcie@2C000000 {
+			compatible = "starfive,jh7110-pcie";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			#interrupt-cells = <1>;
+			reg = <0x0 0x2C000000 0x0 0x1000000>,
+			      <0x9 0xc0000000 0x0 0x10000000>;
+			reg-names = "reg", "config";
+			device_type = "pci";
+			starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,
+				<0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;
+			msi-parent = <&plic>;
+			interrupts = <57>;
+			interrupt-controller;
+			interrupt-names = "msi";
+			interrupt-parent = <&plic>;
+			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
+			interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
+					<0x0 0x0 0x0 0x2 &plic 0x2>,
+					<0x0 0x0 0x0 0x3 &plic 0x3>,
+					<0x0 0x0 0x0 0x4 &plic 0x4>;
+			resets = <&stgcrg JH7110_STGRST_PCIE1_MST0>,
+				 <&stgcrg JH7110_STGRST_PCIE1_SLV0>,
+				 <&stgcrg JH7110_STGRST_PCIE1_SLV>,
+				 <&stgcrg JH7110_STGRST_PCIE1_BRG>,
+				 <&stgcrg JH7110_STGRST_PCIE1_CORE>,
+				 <&stgcrg JH7110_STGRST_PCIE1_APB>;
+			clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
+				 <&stgcrg JH7110_STGCLK_PCIE1_TL>,
+				 <&stgcrg JH7110_STGCLK_PCIE1_AXI>,
+				 <&stgcrg JH7110_STGCLK_PCIE1_APB>;
+			clock-names = "noc_bus_stg_axi", "pcie1_tl", "pcie1_axi", "pcie1_apb";
+			status = "disabled";
+		};
+
 	};
 };