| Message ID | 20230124020818.246755-1-kallisti5@unixzen.com |
|---|---|
| State | Rejected, archived |
| Delegated to: | Andes |
| Headers | show |
| Series | arch/riscv/dts: Fix uart reg-shift on fu540/fu740 SiFive devices | expand |
January 23, 2023 8:08 PM, "Alexander von Gluck IV" <kallisti5@unixzen.com> wrote: > * Not specifying reg-shift creates a situation where the register > shift is unknown and can only be decoded via special compat > cases. > * The device tree specification states: > "...reg-shift. If unspecified, the default value is 0." > https://devicetree-specification.readthedocs.io/en/latest/chapter4-device-bindings.html > * Since the reg-shift for the SiFive boards is *NOT* 0, it shall > be defined as 2 Groan, ignore this patch. I misread somewhere that the sifive,uart0 was 8250 compatible. It is not, and doesn't use any kind of shift other than registers fitting into struct of unions. I'm herding too many cats. -- Alex
diff --git a/arch/riscv/dts/fu540-c000.dtsi b/arch/riscv/dts/fu540-c000.dtsi index 7db8610534..0bea8cf1e5 100644 --- a/arch/riscv/dts/fu540-c000.dtsi +++ b/arch/riscv/dts/fu540-c000.dtsi @@ -161,6 +161,7 @@ uart0: serial@10010000 { compatible = "sifive,fu540-c000-uart", "sifive,uart0"; reg = <0x0 0x10010000 0x0 0x1000>; + reg-shift = <2>; interrupt-parent = <&plic0>; interrupts = <4>; clocks = <&prci PRCI_CLK_TLCLK>; diff --git a/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi index 7b77c13496..19da3709f0 100644 --- a/arch/riscv/dts/fu740-c000.dtsi +++ b/arch/riscv/dts/fu740-c000.dtsi @@ -164,6 +164,7 @@ uart0: serial@10010000 { compatible = "sifive,fu740-c000-uart", "sifive,uart0"; reg = <0x0 0x10010000 0x0 0x1000>; + reg-shift = <2>; interrupt-parent = <&plic0>; interrupts = <39>; clocks = <&prci FU740_PRCI_CLK_PCLK>; @@ -172,6 +173,7 @@ uart1: serial@10011000 { compatible = "sifive,fu740-c000-uart", "sifive,uart0"; reg = <0x0 0x10011000 0x0 0x1000>; + reg-shift = <2>; interrupt-parent = <&plic0>; interrupts = <40>; clocks = <&prci FU740_PRCI_CLK_PCLK>;