| Message ID | 20230117165241.5853-3-clamor95@gmail.com |
|---|---|
| State | Superseded |
| Delegated to: | Tom Warren |
| Headers | show |
| Series | Re-Send Timer support for ARM Tegra | expand |
Hi Svyatoslav, On Tue, 17 Jan 2023 at 09:53, Svyatoslav Ryhel <clamor95@gmail.com> wrote: > > Add timer support for T20/T30/T114 and T124 based devices. > Driver is based on DM, has device tree support and can be > used on SPL and early boot stage. > > Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 > Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 > Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 > Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 > Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> > Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> > --- > drivers/timer/Kconfig | 8 +++ > drivers/timer/Makefile | 1 + > drivers/timer/tegra-timer.c | 124 ++++++++++++++++++++++++++++++++++++ > 3 files changed, 133 insertions(+) > create mode 100644 drivers/timer/tegra-timer.c > > diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig > index 6d6665005c..f32bd16227 100644 > --- a/drivers/timer/Kconfig > +++ b/drivers/timer/Kconfig > @@ -252,6 +252,14 @@ config STM32_TIMER > Select this to enable support for the timer found on > STM32 devices. > > +config TEGRA_TIMER > + bool "Tegra timer support" > + depends on TIMER > + select TIMER_EARLY > + help > + Select this to enable support for the timer found on > + Tegra devices. > + > config X86_TSC_TIMER > bool "x86 Time-Stamp Counter (TSC) timer support" > depends on TIMER && X86 > diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile > index 6470fd5426..3c92113fc6 100644 > --- a/drivers/timer/Makefile > +++ b/drivers/timer/Makefile > @@ -27,6 +27,7 @@ obj-$(CONFIG_SP804_TIMER) += sp804_timer.o > obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o > obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o > obj-$(CONFIG_STM32_TIMER) += stm32_timer.o > +obj-$(CONFIG_TEGRA_TIMER) += tegra-timer.o > obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o > obj-$(CONFIG_MTK_TIMER) += mtk_timer.o > obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o > diff --git a/drivers/timer/tegra-timer.c b/drivers/timer/tegra-timer.c > new file mode 100644 > index 0000000000..cda460921f > --- /dev/null > +++ b/drivers/timer/tegra-timer.c > @@ -0,0 +1,124 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright (C) 2022 Svyatoslav Ryhel <clamor95@gmail.com> > + */ > + > +#include <common.h> > +#include <dm.h> > +#include <errno.h> > +#include <timer.h> > + > +#include <asm/io.h> > +#include <asm/arch/clock.h> > +#include <asm/arch/tegra.h> > + > +#define TEGRA_OSC_CLK_ENB_L_SET (NV_PA_CLK_RST_BASE + 0x320) > +#define TEGRA_OSC_SET_CLK_ENB_TMR BIT(5) > + > +#define TEGRA_TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0) > +#define TEGRA_TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4) > + > +#define TEGRA_TIMER_RATE 1000000 /* 1 MHz */ > + > +u64 notrace timer_early_get_count(void) > +{ > + /* At this stage raw timer is used */ > + return readl(TEGRA_TIMER_USEC_CNTR); > +} > + > +unsigned long notrace timer_early_get_rate(void) > +{ > + return TEGRA_TIMER_RATE; > +} > + > +#if CONFIG_IS_ENABLED(BOOTSTAGE) You shouldn't need the #ifdef as the code will just be dropped by the linker if not used. > +ulong timer_get_boot_us(void) > +{ > + u64 ticks = 0; > + int ret; > + > + ret = dm_timer_init(); You can't call this here since tracing and bootstage won't work (they need the timer before driver model starts) . You can check gd->timer and use the early one or the driver model one. > + if (!ret) > + timer_get_count(gd->timer, &ticks); > + else > + ticks = timer_early_get_count(); > + > + return ticks; > +} > +#endif > + > +static notrace u64 tegra_timer_get_count(struct udevice *dev) > +{ > + u32 val = timer_early_get_count(); > + return timer_conv_64(val); > +} > + [..] Regards, Simon
вт, 17 січ. 2023 р. о 22:30 Simon Glass <sjg@chromium.org> пише: > > Hi Svyatoslav, > > On Tue, 17 Jan 2023 at 09:53, Svyatoslav Ryhel <clamor95@gmail.com> wrote: > > > > Add timer support for T20/T30/T114 and T124 based devices. > > Driver is based on DM, has device tree support and can be > > used on SPL and early boot stage. > > > > Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 > > Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 > > Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 > > Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 > > Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> > > Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> > > --- > > drivers/timer/Kconfig | 8 +++ > > drivers/timer/Makefile | 1 + > > drivers/timer/tegra-timer.c | 124 ++++++++++++++++++++++++++++++++++++ > > 3 files changed, 133 insertions(+) > > create mode 100644 drivers/timer/tegra-timer.c > > > > diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig > > index 6d6665005c..f32bd16227 100644 > > --- a/drivers/timer/Kconfig > > +++ b/drivers/timer/Kconfig > > @@ -252,6 +252,14 @@ config STM32_TIMER > > Select this to enable support for the timer found on > > STM32 devices. > > > > +config TEGRA_TIMER > > + bool "Tegra timer support" > > + depends on TIMER > > + select TIMER_EARLY > > + help > > + Select this to enable support for the timer found on > > + Tegra devices. > > + > > config X86_TSC_TIMER > > bool "x86 Time-Stamp Counter (TSC) timer support" > > depends on TIMER && X86 > > diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile > > index 6470fd5426..3c92113fc6 100644 > > --- a/drivers/timer/Makefile > > +++ b/drivers/timer/Makefile > > @@ -27,6 +27,7 @@ obj-$(CONFIG_SP804_TIMER) += sp804_timer.o > > obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o > > obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o > > obj-$(CONFIG_STM32_TIMER) += stm32_timer.o > > +obj-$(CONFIG_TEGRA_TIMER) += tegra-timer.o > > obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o > > obj-$(CONFIG_MTK_TIMER) += mtk_timer.o > > obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o > > diff --git a/drivers/timer/tegra-timer.c b/drivers/timer/tegra-timer.c > > new file mode 100644 > > index 0000000000..cda460921f > > --- /dev/null > > +++ b/drivers/timer/tegra-timer.c > > @@ -0,0 +1,124 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright (C) 2022 Svyatoslav Ryhel <clamor95@gmail.com> > > + */ > > + > > +#include <common.h> > > +#include <dm.h> > > +#include <errno.h> > > +#include <timer.h> > > + > > +#include <asm/io.h> > > +#include <asm/arch/clock.h> > > +#include <asm/arch/tegra.h> > > + > > +#define TEGRA_OSC_CLK_ENB_L_SET (NV_PA_CLK_RST_BASE + 0x320) > > +#define TEGRA_OSC_SET_CLK_ENB_TMR BIT(5) > > + > > +#define TEGRA_TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0) > > +#define TEGRA_TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4) > > + > > +#define TEGRA_TIMER_RATE 1000000 /* 1 MHz */ > > + > > +u64 notrace timer_early_get_count(void) > > +{ > > + /* At this stage raw timer is used */ > > + return readl(TEGRA_TIMER_USEC_CNTR); > > +} > > + > > +unsigned long notrace timer_early_get_rate(void) > > +{ > > + return TEGRA_TIMER_RATE; > > +} > > + > > +#if CONFIG_IS_ENABLED(BOOTSTAGE) > > You shouldn't need the #ifdef as the code will just be dropped by the > linker if not used. Hello Simon! Thank you for your review! Will do in V4 > > > +ulong timer_get_boot_us(void) > > +{ > > + u64 ticks = 0; > > + int ret; > > + > > + ret = dm_timer_init(); > > You can't call this here since tracing and bootstage won't work (they > need the timer before driver model starts) . You can check gd->timer > and use the early one or the driver model one. Timer is tricky because it has to be active one of the first. I consider using here early version unconditionally would be the best option. Will update in V4 Best regards, Svyatoslav R. > > > + if (!ret) > > + timer_get_count(gd->timer, &ticks); > > + else > > + ticks = timer_early_get_count(); > > + > > + return ticks; > > +} > > +#endif > > + > > +static notrace u64 tegra_timer_get_count(struct udevice *dev) > > +{ > > + u32 val = timer_early_get_count(); > > + return timer_conv_64(val); > > +} > > + > [..] > > Regards, > Simon
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig index 6d6665005c..f32bd16227 100644 --- a/drivers/timer/Kconfig +++ b/drivers/timer/Kconfig @@ -252,6 +252,14 @@ config STM32_TIMER Select this to enable support for the timer found on STM32 devices. +config TEGRA_TIMER + bool "Tegra timer support" + depends on TIMER + select TIMER_EARLY + help + Select this to enable support for the timer found on + Tegra devices. + config X86_TSC_TIMER bool "x86 Time-Stamp Counter (TSC) timer support" depends on TIMER && X86 diff --git a/drivers/timer/Makefile b/drivers/timer/Makefile index 6470fd5426..3c92113fc6 100644 --- a/drivers/timer/Makefile +++ b/drivers/timer/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_SP804_TIMER) += sp804_timer.o obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint_timer.o obj-$(CONFIG_ARM_GLOBAL_TIMER) += arm_global_timer.o obj-$(CONFIG_STM32_TIMER) += stm32_timer.o +obj-$(CONFIG_TEGRA_TIMER) += tegra-timer.o obj-$(CONFIG_X86_TSC_TIMER) += tsc_timer.o obj-$(CONFIG_MTK_TIMER) += mtk_timer.o obj-$(CONFIG_MCHP_PIT64B_TIMER) += mchp-pit64b-timer.o diff --git a/drivers/timer/tegra-timer.c b/drivers/timer/tegra-timer.c new file mode 100644 index 0000000000..cda460921f --- /dev/null +++ b/drivers/timer/tegra-timer.c @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2022 Svyatoslav Ryhel <clamor95@gmail.com> + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <timer.h> + +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/tegra.h> + +#define TEGRA_OSC_CLK_ENB_L_SET (NV_PA_CLK_RST_BASE + 0x320) +#define TEGRA_OSC_SET_CLK_ENB_TMR BIT(5) + +#define TEGRA_TIMER_USEC_CNTR (NV_PA_TMRUS_BASE + 0) +#define TEGRA_TIMER_USEC_CFG (NV_PA_TMRUS_BASE + 4) + +#define TEGRA_TIMER_RATE 1000000 /* 1 MHz */ + +u64 notrace timer_early_get_count(void) +{ + /* At this stage raw timer is used */ + return readl(TEGRA_TIMER_USEC_CNTR); +} + +unsigned long notrace timer_early_get_rate(void) +{ + return TEGRA_TIMER_RATE; +} + +#if CONFIG_IS_ENABLED(BOOTSTAGE) +ulong timer_get_boot_us(void) +{ + u64 ticks = 0; + int ret; + + ret = dm_timer_init(); + if (!ret) + timer_get_count(gd->timer, &ticks); + else + ticks = timer_early_get_count(); + + return ticks; +} +#endif + +static notrace u64 tegra_timer_get_count(struct udevice *dev) +{ + u32 val = timer_early_get_count(); + return timer_conv_64(val); +} + +static int tegra_timer_probe(struct udevice *dev) +{ + struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); + u32 usec_config, value; + + /* Timer rate has to be set unconditionally */ + uc_priv->clock_rate = TEGRA_TIMER_RATE; + + /* + * Configure microsecond timers to have 1MHz clock + * Config register is 0xqqww, where qq is "dividend", ww is "divisor" + * Uses n+1 scheme + */ + switch (clock_get_osc_freq()) { + case CLOCK_OSC_FREQ_13_0: + usec_config = 0x000c; /* (12+1)/(0+1) */ + break; + case CLOCK_OSC_FREQ_19_2: + usec_config = 0x045f; /* (95+1)/(4+1) */ + break; + case CLOCK_OSC_FREQ_12_0: + usec_config = 0x000b; /* (11+1)/(0+1) */ + break; + case CLOCK_OSC_FREQ_26_0: + usec_config = 0x0019; /* (25+1)/(0+1) */ + break; + case CLOCK_OSC_FREQ_16_8: + usec_config = 0x0453; /* (83+1)/(4+1) */ + break; + case CLOCK_OSC_FREQ_38_4: + usec_config = 0x04bf; /* (191+1)/(4+1) */ + break; + case CLOCK_OSC_FREQ_48_0: + usec_config = 0x002f; /* (47+1)/(0+1) */ + break; + default: + return -EINVAL; + } + + /* Enable clock to timer hardware */ + value = readl_relaxed(TEGRA_OSC_CLK_ENB_L_SET); + writel_relaxed(value | TEGRA_OSC_SET_CLK_ENB_TMR, + TEGRA_OSC_CLK_ENB_L_SET); + + writel_relaxed(usec_config, TEGRA_TIMER_USEC_CFG); + + return 0; +} + +static const struct timer_ops tegra_timer_ops = { + .get_count = tegra_timer_get_count, +}; + +static const struct udevice_id tegra_timer_ids[] = { + { .compatible = "nvidia,tegra20-timer" }, + { .compatible = "nvidia,tegra30-timer" }, + { .compatible = "nvidia,tegra114-timer" }, + { .compatible = "nvidia,tegra124-timer" }, + { } +}; + +U_BOOT_DRIVER(tegra_timer) = { + .name = "tegra_timer", + .id = UCLASS_TIMER, + .of_match = tegra_timer_ids, + .probe = tegra_timer_probe, + .ops = &tegra_timer_ops, + .flags = DM_FLAG_PRE_RELOC, +};