diff mbox series

[v4,23/25] ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2) IO

Message ID 20221214175111.477134-24-jagan@edgeble.ai
State Accepted
Commit 0736dad4edc044a9e5804cc40ff18148dfe9e607
Delegated to: Kever Yang
Headers show
Series ARM: Add Rockchip RV1126 support | expand

Commit Message

Jagan Teki Dec. 14, 2022, 5:51 p.m. UTC
Neural Compute Module 2(Neu2) IO board is an industrial form factor
evaluation board from Edgeble AI.

General features:
- microSD slot
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC battery slot
- 40-pin expansion

Neu2 needs to mount on top of this IO board in order to create complete
Edgeble Neural Compute Module 2(Neu2) IO platform.

Add support for it.

Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Changes for v4:
- pick changes from linux
Changes for v3:
- rebase on linux
Changes for v2:
- none

 arch/arm/dts/Makefile                   |  3 ++
 arch/arm/dts/rv1126-edgeble-neu2-io.dts | 42 +++++++++++++++++++++++++
 2 files changed, 45 insertions(+)
 create mode 100644 arch/arm/dts/rv1126-edgeble-neu2-io.dts

Comments

Kever Yang Dec. 18, 2022, 10:40 a.m. UTC | #1
On 2022/12/15 01:51, Jagan Teki wrote:
> Neural Compute Module 2(Neu2) IO board is an industrial form factor
> evaluation board from Edgeble AI.
>
> General features:
> - microSD slot
> - MIPI DSI connector
> - 2x USB Host
> - 1x USB OTG
> - Ethernet
> - mini PCIe
> - Onboard PoE
> - RS485, RS232, CAN
> - Micro Phone array
> - Speaker
> - RTC battery slot
> - 40-pin expansion
>
> Neu2 needs to mount on top of this IO board in order to create complete
> Edgeble Neural Compute Module 2(Neu2) IO platform.
>
> Add support for it.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
> Changes for v4:
> - pick changes from linux
> Changes for v3:
> - rebase on linux
> Changes for v2:
> - none
>
>   arch/arm/dts/Makefile                   |  3 ++
>   arch/arm/dts/rv1126-edgeble-neu2-io.dts | 42 +++++++++++++++++++++++++
>   2 files changed, 45 insertions(+)
>   create mode 100644 arch/arm/dts/rv1126-edgeble-neu2-io.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 43951a7731..a0ea23113c 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -170,6 +170,9 @@ dtb-$(CONFIG_ROCKCHIP_RV1108) += \
>   	rv1108-elgin-r1.dtb \
>   	rv1108-evb.dtb
>   
> +dtb-$(CONFIG_ROCKCHIP_RV1126) += \
> +	rv1126-edgeble-neu2-io.dtb
> +
>   dtb-$(CONFIG_ARCH_S5P4418) += \
>   	s5p4418-nanopi2.dtb
>   
> diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
> new file mode 100644
> index 0000000000..dded0a12f0
> --- /dev/null
> +++ b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
> @@ -0,0 +1,42 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
> + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
> + */
> +
> +/dts-v1/;
> +#include "rv1126.dtsi"
> +#include "rv1126-edgeble-neu2.dtsi"
> +
> +/ {
> +	model = "Edgeble Neu2 IO Board";
> +	compatible = "edgeble,neural-compute-module-2-io",
> +		     "edgeble,neural-compute-module-2", "rockchip,rv1126";
> +
> +	aliases {
> +		serial2 = &uart2;
> +	};
> +
> +	chosen {
> +		stdout-path = "serial2:1500000n8";
> +	};
> +};
> +
> +&sdmmc {
> +	bus-width = <4>;
> +	cap-mmc-highspeed;
> +	cap-sd-highspeed;
> +	card-detect-delay = <200>;
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
> +	rockchip,default-sample-phase = <90>;
> +	sd-uhs-sdr12;
> +	sd-uhs-sdr25;
> +	sd-uhs-sdr104;
> +	vqmmc-supply = <&vccio_sd>;
> +	status = "okay";
> +};
> +
> +&uart2 {
> +	status = "okay";
> +};
diff mbox series

Patch

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 43951a7731..a0ea23113c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -170,6 +170,9 @@  dtb-$(CONFIG_ROCKCHIP_RV1108) += \
 	rv1108-elgin-r1.dtb \
 	rv1108-evb.dtb
 
+dtb-$(CONFIG_ROCKCHIP_RV1126) += \
+	rv1126-edgeble-neu2-io.dtb
+
 dtb-$(CONFIG_ARCH_S5P4418) += \
 	s5p4418-nanopi2.dtb
 
diff --git a/arch/arm/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
new file mode 100644
index 0000000000..dded0a12f0
--- /dev/null
+++ b/arch/arm/dts/rv1126-edgeble-neu2-io.dts
@@ -0,0 +1,42 @@ 
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/dts-v1/;
+#include "rv1126.dtsi"
+#include "rv1126-edgeble-neu2.dtsi"
+
+/ {
+	model = "Edgeble Neu2 IO Board";
+	compatible = "edgeble,neural-compute-module-2-io",
+		     "edgeble,neural-compute-module-2", "rockchip,rv1126";
+
+	aliases {
+		serial2 = &uart2;
+	};
+
+	chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+};
+
+&sdmmc {
+	bus-width = <4>;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	card-detect-delay = <200>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
+	rockchip,default-sample-phase = <90>;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr104;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};