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[1/2] arch: arm: mach-socfpga: Use custom header target buffer in SPL

Message ID 20220902015809.4889-2-sieu.mun.tang@intel.com
State Needs Review / ACK, archived
Delegated to: Marek Vasut
Headers show
Series *** SUBJECT HERE *** | expand

Commit Message

Sieu Mun Tang Sept. 2, 2022, 1:58 a.m. UTC 
From: Tien Fong Chee <tien.fong.chee@intel.com>

Allocate buffer from bottom half of DDR for the image headers in SPL on
Arria10. This allows SPL to load the fitImage header, parse it,
extract the FPGA core bitstream section from it, and program the FPGA.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
---
 arch/arm/mach-socfpga/spl_a10.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)
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Patch

diff --git a/arch/arm/mach-socfpga/spl_a10.c b/arch/arm/mach-socfpga/spl_a10.c
index ec67a5b0eb..bfcbd1dfe1 100644
--- a/arch/arm/mach-socfpga/spl_a10.c
+++ b/arch/arm/mach-socfpga/spl_a10.c
@@ -28,6 +28,8 @@ 
 #include <watchdog.h>
 #include <asm/arch/pinmux.h>
 #include <asm/arch/fpga_manager.h>
+#include <exports.h>
+#include <log.h>
 #include <mmc.h>
 #include <memalign.h>
 #include <linux/delay.h>
@@ -281,3 +283,13 @@  void spl_board_prepare_for_boot(void)
 	writel(FSBL_IMAGE_IS_VALID, socfpga_get_sysmgr_addr() +
 	       SYSMGR_A10_ROMCODE_INITSWSTATE);
 }
+
+#if defined(CONFIG_SPL_LOAD_FIT) && defined(CONFIG_SPL_SPI_LOAD)
+struct image_header *spl_get_load_buffer(int offset, size_t size)
+{
+	if (gd->ram_size)
+		return (struct image_header *)(gd->ram_size / 2);
+	else
+		return NULL;
+}
+#endif