| Message ID | 20220128081152.14901-13-a-govindraju@ti.com |
|---|---|
| State | Accepted |
| Commit | 3c1d89ff76e26765691eb17f5d2fd9f384890010 |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | SIERRA: Add support for Mulitlink Configuration | expand |
On Fri, Jan 28, 2022 at 01:41:39PM +0530, Aswath Govindraju wrote: > The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the > function device_probe, the corresponding clocks are probed before calling > the device's probe. The PLL_CMNLC mux clock can only be created after the > device's probe. Therefore, move assigned-clocks and assigned-clock-parents > to the link nodes in U-Boot device tree file. > > Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Applied to u-boot/master, thanks!
diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index 3ca9b5c801f0..938e978a6b66 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -232,3 +232,13 @@ &usb_serdes_mux { u-boot,mux-autoprobe; }; + +&serdes0 { + /delete-property/ assigned-clocks; + /delete-property/ assigned-clock-parents; +}; + +&serdes0_pcie_link { + assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>; + assigned-clock-parents = <&wiz0_pll1_refclk>; +}; diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts index 4b2362a5dd05..8299463c3e01 100644 --- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts +++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts @@ -8,6 +8,7 @@ #include "k3-j721e-som-p0.dtsi" #include "k3-j721e-ddr-evm-lp4-4266.dtsi" #include "k3-j721e-ddr.dtsi" +#include <dt-bindings/phy/phy-cadence.h> / { aliases { @@ -361,3 +362,26 @@ &mcu_udmap { ti,sci = <&dm_tifs>; }; + +&wiz0_pll1_refclk { + assigned-clocks = <&wiz0_pll1_refclk>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&wiz0_refclk_dig { + assigned-clocks = <&wiz0_refclk_dig>; + assigned-clock-parents = <&cmn_refclk1>; +}; + +&serdes0 { + assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>; + assigned-clock-parents = <&wiz0_pll1_refclk>; + + serdes0_pcie_link: link@0 { + reg = <0>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = <PHY_TYPE_PCIE>; + resets = <&serdes_wiz0 1>; + }; +};
The PLL_CMNLC clocks are modelled as a child clock device of seirra. In the function device_probe, the corresponding clocks are probed before calling the device's probe. The PLL_CMNLC mux clock can only be created after the device's probe. Therefore, move assigned-clocks and assigned-clock-parents to the link nodes in U-Boot device tree file. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> --- .../k3-j721e-common-proc-board-u-boot.dtsi | 10 ++++++++ .../arm/dts/k3-j721e-r5-common-proc-board.dts | 24 +++++++++++++++++++ 2 files changed, 34 insertions(+)