diff mbox series

[v2,09/20] ram: k3-ddrss: Add support for J721S2 SoC

Message ID 20220111075545.1880-10-a-govindraju@ti.com
State Changes Requested
Delegated to: Tom Rini
Headers show
Series J721S2: Add initial support | expand

Commit Message

Aswath Govindraju Jan. 11, 2022, 7:55 a.m. UTC 
From: David Huang <d-huang@ti.com>

Add support for DDR subsystem in J721S2 SoC.

Signed-off-by: David Huang <d-huang@ti.com>
Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
 drivers/ram/Kconfig           | 12 ++++++++++++
 drivers/ram/k3-ddrss/Makefile |  4 ++++
 2 files changed, 16 insertions(+)

Comments

Tom Rini Jan. 13, 2022, 2:15 p.m. UTC | #1 
On Tue, Jan 11, 2022 at 01:25:34PM +0530, Aswath Govindraju wrote:

> From: David Huang <d-huang@ti.com>
> 
> Add support for DDR subsystem in J721S2 SoC.
> 
> Signed-off-by: David Huang <d-huang@ti.com>
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
> ---
>  drivers/ram/Kconfig           | 12 ++++++++++++
>  drivers/ram/k3-ddrss/Makefile |  4 ++++
>  2 files changed, 16 insertions(+)
> 
> diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
> index a79594d35198..2b6b1d57aaaa 100644
> --- a/drivers/ram/Kconfig
> +++ b/drivers/ram/Kconfig
> @@ -63,6 +63,7 @@ choice
>  	prompt "K3 DDRSS Arch Support"
>  
>  	default K3_J721E_DDRSS if SOC_K3_J721E
> +	default K3_J721S2_DDRSS if SOC_K3_J721S2
>  	default K3_AM64_DDRSS if SOC_K3_AM642
>  
>  config K3_J721E_DDRSS
> @@ -75,6 +76,17 @@ config K3_J721E_DDRSS
>  	  Enabling this config adds support for the DDR memory controller
>  	  on J721E family of SoCs.
>  
> +config K3_J721S2_DDRSS
> +	bool "Enable J721S2 DRSS support"
> +	help
> +	  The J721S2 DDR subsystem comprises DDR controller, DDR PHY and
> +	  wrapper logic to integrate these blocks in the device. The DDR
> +	  subsystem is used to provide an interface to external SDRAM
> +	  devices which can be utilized for storing program or data.
> +	  Enabling this config adds support for the DDR memory controller
> +	  on J721S2 family of SoCs.
> +
> +
>  config K3_AM64_DDRSS
>  	bool "Enable AM64 DDRSS support"
>  	help
> diff --git a/drivers/ram/k3-ddrss/Makefile b/drivers/ram/k3-ddrss/Makefile
> index 8be00118f501..d30bf5ec6dab 100644
> --- a/drivers/ram/k3-ddrss/Makefile
> +++ b/drivers/ram/k3-ddrss/Makefile
> @@ -15,3 +15,7 @@ ccflags-$(CONFIG_K3_AM64_DDRSS) += -Idrivers/ram/k3-ddrss/16bit/
>  obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit.o
>  obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit_ctl_regs_rw_masks.o
>  ccflags-$(CONFIG_K3_J721E_DDRSS) += -Idrivers/ram/k3-ddrss/32bit/
> +
> +obj-$(CONFIG_K3_J721S2_DDRSS) += lpddr4_32bit.o
> +obj-$(CONFIG_K3_J721S2_DDRSS) += lpddr4_32bit_ctl_regs_rw_masks.o
> +ccflags-$(CONFIG_K3_J721S2_DDRSS) += -Idrivers/ram/k3-ddrss/32bit/

I'm not seeing a difference between J721E and J721S2 here.  This tells
me the symbol should be renamed and almost certainly select'd by the SoC
and not asked to the user, as well.
Aswath Govindraju Jan. 17, 2022, 6:31 a.m. UTC | #2 
Hi Tom,

On 13/01/22 7:45 pm, Tom Rini wrote:
> On Tue, Jan 11, 2022 at 01:25:34PM +0530, Aswath Govindraju wrote:
> 
>> From: David Huang <d-huang@ti.com>
>>
>> Add support for DDR subsystem in J721S2 SoC.
>>
>> Signed-off-by: David Huang <d-huang@ti.com>
>> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
>> ---
>>  drivers/ram/Kconfig           | 12 ++++++++++++
>>  drivers/ram/k3-ddrss/Makefile |  4 ++++
>>  2 files changed, 16 insertions(+)
>>
>> diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
>> index a79594d35198..2b6b1d57aaaa 100644
>> --- a/drivers/ram/Kconfig
>> +++ b/drivers/ram/Kconfig
>> @@ -63,6 +63,7 @@ choice
>>  	prompt "K3 DDRSS Arch Support"
>>  
>>  	default K3_J721E_DDRSS if SOC_K3_J721E
>> +	default K3_J721S2_DDRSS if SOC_K3_J721S2
>>  	default K3_AM64_DDRSS if SOC_K3_AM642
>>  
>>  config K3_J721E_DDRSS
>> @@ -75,6 +76,17 @@ config K3_J721E_DDRSS
>>  	  Enabling this config adds support for the DDR memory controller
>>  	  on J721E family of SoCs.
>>  
>> +config K3_J721S2_DDRSS
>> +	bool "Enable J721S2 DRSS support"
>> +	help
>> +	  The J721S2 DDR subsystem comprises DDR controller, DDR PHY and
>> +	  wrapper logic to integrate these blocks in the device. The DDR
>> +	  subsystem is used to provide an interface to external SDRAM
>> +	  devices which can be utilized for storing program or data.
>> +	  Enabling this config adds support for the DDR memory controller
>> +  on J721S2 family of SoCs.
>> +
>> +
>>  config K3_AM64_DDRSS
>>  	bool "Enable AM64 DDRSS support"
>>  	help
>> diff --git a/drivers/ram/k3-ddrss/Makefile b/drivers/ram/k3-ddrss/Makefile
>> index 8be00118f501..d30bf5ec6dab 100644
>> --- a/drivers/ram/k3-ddrss/Makefile
>> +++ b/drivers/ram/k3-ddrss/Makefile
>> @@ -15,3 +15,7 @@ ccflags-$(CONFIG_K3_AM64_DDRSS) += -Idrivers/ram/k3-ddrss/16bit/
>>  obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit.o
>>  obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit_ctl_regs_rw_masks.o
>>  ccflags-$(CONFIG_K3_J721E_DDRSS) += -Idrivers/ram/k3-ddrss/32bit/
>> +
>> +obj-$(CONFIG_K3_J721S2_DDRSS) += lpddr4_32bit.o
>> +obj-$(CONFIG_K3_J721S2_DDRSS) += lpddr4_32bit_ctl_regs_rw_masks.o
>> +ccflags-$(CONFIG_K3_J721S2_DDRSS) += -Idrivers/ram/k3-ddrss/32bit/
> 
> I'm not seeing a difference between J721E and J721S2 here.  This tells
> me the symbol should be renamed and almost certainly select'd by the SoC
> and not asked to the user, as well.
> 

I'll use the config K3_J721E_DDRSS for j721s2 as well and select it by
default based on the SoC.

Thanks,
Aswath
diff mbox series

Patch

diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index a79594d35198..2b6b1d57aaaa 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -63,6 +63,7 @@  choice
 	prompt "K3 DDRSS Arch Support"
 
 	default K3_J721E_DDRSS if SOC_K3_J721E
+	default K3_J721S2_DDRSS if SOC_K3_J721S2
 	default K3_AM64_DDRSS if SOC_K3_AM642
 
 config K3_J721E_DDRSS
@@ -75,6 +76,17 @@  config K3_J721E_DDRSS
 	  Enabling this config adds support for the DDR memory controller
 	  on J721E family of SoCs.
 
+config K3_J721S2_DDRSS
+	bool "Enable J721S2 DRSS support"
+	help
+	  The J721S2 DDR subsystem comprises DDR controller, DDR PHY and
+	  wrapper logic to integrate these blocks in the device. The DDR
+	  subsystem is used to provide an interface to external SDRAM
+	  devices which can be utilized for storing program or data.
+	  Enabling this config adds support for the DDR memory controller
+	  on J721S2 family of SoCs.
+
+
 config K3_AM64_DDRSS
 	bool "Enable AM64 DDRSS support"
 	help
diff --git a/drivers/ram/k3-ddrss/Makefile b/drivers/ram/k3-ddrss/Makefile
index 8be00118f501..d30bf5ec6dab 100644
--- a/drivers/ram/k3-ddrss/Makefile
+++ b/drivers/ram/k3-ddrss/Makefile
@@ -15,3 +15,7 @@  ccflags-$(CONFIG_K3_AM64_DDRSS) += -Idrivers/ram/k3-ddrss/16bit/
 obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit.o
 obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit_ctl_regs_rw_masks.o
 ccflags-$(CONFIG_K3_J721E_DDRSS) += -Idrivers/ram/k3-ddrss/32bit/
+
+obj-$(CONFIG_K3_J721S2_DDRSS) += lpddr4_32bit.o
+obj-$(CONFIG_K3_J721S2_DDRSS) += lpddr4_32bit_ctl_regs_rw_masks.o
+ccflags-$(CONFIG_K3_J721S2_DDRSS) += -Idrivers/ram/k3-ddrss/32bit/