| Message ID | 20211127125235.30577-1-radu-andrei.bulie@nxp.com |
|---|---|
| State | Accepted |
| Commit | 8c1a6957b13e5c624b015b0e91d4445a76b72eaf |
| Delegated to: | Ramon Fried |
| Headers | show |
| Series | drivers: net: Soft reset felix switch core | expand |
On Sat, Nov 27, 2021 at 5:06 PM Vladimir Oltean <vladimir.oltean@nxp.com> wrote: > > On Sat, Nov 27, 2021 at 02:52:35PM +0200, Radu Bulie wrote: > > It turns out that in custom designs if the system is reset > > multiple times in conjunction with a slight increase in external > > temperature, the felix switch starts to behave in a strange way: > > packets are no longer received on the ENECT interface connected > > to the L2switch internal port (the TX side of internal port stops working > > or the packets do not reach there. It is not very clear where > > the packets remain blocked. None of the counters points to a disruption > > in the L2switch) > > The issue is not reproducible on NXP reference designs. > > > > It was observed that by adding the switch core reset, the problem > > goes aways, even if intensive testing in temperature chambers > > is applied. > > > > The current patch performs soft reset on the switch core to ensure proper > > operation of the L2switch. > > > > Signed-off-by: Radu Bulie <radu-andrei.bulie@nxp.com> > > --- > > Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> > > Thanks! Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
On Sat, Nov 27, 2021 at 9:36 PM Ramon Fried <rfried.dev@gmail.com> wrote: > > On Sat, Nov 27, 2021 at 5:06 PM Vladimir Oltean <vladimir.oltean@nxp.com> wrote: > > > > On Sat, Nov 27, 2021 at 02:52:35PM +0200, Radu Bulie wrote: > > > It turns out that in custom designs if the system is reset > > > multiple times in conjunction with a slight increase in external > > > temperature, the felix switch starts to behave in a strange way: > > > packets are no longer received on the ENECT interface connected > > > to the L2switch internal port (the TX side of internal port stops working > > > or the packets do not reach there. It is not very clear where > > > the packets remain blocked. None of the counters points to a disruption > > > in the L2switch) > > > The issue is not reproducible on NXP reference designs. > > > > > > It was observed that by adding the switch core reset, the problem > > > goes aways, even if intensive testing in temperature chambers > > > is applied. > > > > > > The current patch performs soft reset on the switch core to ensure proper > > > operation of the L2switch. > > > > > > Signed-off-by: Radu Bulie <radu-andrei.bulie@nxp.com> > > > --- > > > > Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> > > > > Thanks! > Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Applied to u-boot-net/next, Thanks.
diff --git a/drivers/net/mscc_eswitch/felix_switch.c b/drivers/net/mscc_eswitch/felix_switch.c index 2df8dde55f..60b2e8f32d 100644 --- a/drivers/net/mscc_eswitch/felix_switch.c +++ b/drivers/net/mscc_eswitch/felix_switch.c @@ -40,7 +40,9 @@ #define FELIX_IS2 0x060000 #define FELIX_GMII(port) (0x100000 + (port) * 0x10000) #define FELIX_QSYS 0x200000 - +#define FELIX_DEVCPU_GCB 0x070000 +#define FELIX_DEVCPU_GCB_SOFT_RST (FELIX_DEVCPU_GCB + 0x00000004) +#define SOFT_SWC_RST BIT(0) #define FELIX_SYS_SYSTEM (FELIX_SYS + 0x00000E00) #define FELIX_SYS_SYSTEM_EN BIT(0) #define FELIX_SYS_RAM_CTRL (FELIX_SYS + 0x00000F24) @@ -237,6 +239,15 @@ static void felix_init(struct udevice *dev) void *base = priv->regs_base; int timeout = 100; + /* Switch core reset */ + out_le32(base + FELIX_DEVCPU_GCB_SOFT_RST, SOFT_SWC_RST); + while (in_le32(base + FELIX_DEVCPU_GCB_SOFT_RST) & SOFT_SWC_RST && + --timeout) + udelay(10); + if (in_le32(base + FELIX_DEVCPU_GCB_SOFT_RST) & SOFT_SWC_RST) + dev_err(dev, "Timeout waiting for switch core reset\n"); + timeout = 100; + /* Init core memories */ out_le32(base + FELIX_SYS_RAM_CTRL, FELIX_SYS_RAM_CTRL_INIT); while (in_le32(base + FELIX_SYS_RAM_CTRL) & FELIX_SYS_RAM_CTRL_INIT &&
It turns out that in custom designs if the system is reset multiple times in conjunction with a slight increase in external temperature, the felix switch starts to behave in a strange way: packets are no longer received on the ENECT interface connected to the L2switch internal port (the TX side of internal port stops working or the packets do not reach there. It is not very clear where the packets remain blocked. None of the counters points to a disruption in the L2switch) The issue is not reproducible on NXP reference designs. It was observed that by adding the switch core reset, the problem goes aways, even if intensive testing in temperature chambers is applied. The current patch performs soft reset on the switch core to ensure proper operation of the L2switch. Signed-off-by: Radu Bulie <radu-andrei.bulie@nxp.com> --- drivers/net/mscc_eswitch/felix_switch.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-)