diff mbox series

[v2,2/5] arm: mach-k3: j7200: Fix clk-data parenting for postdiv PLL clocks

Message ID 20210907221658.12428-3-d-gerlach@ti.com
State Accepted
Commit 326c03b5482037d3c5b697dd588dfebb701d33b2
Delegated to: Tom Rini
Headers show
Series arm: mach-k3: Fixes for j721e/j7200 clock data and drivers | expand

Commit Message

Dave Gerlach Sept. 7, 2021, 10:16 p.m. UTC 
From: Suman Anna <s-anna@ti.com>

The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
divisors to generate the final FOUTPOSTDIV clock. These are in sequence
with POSTDIV2 following the POSTDIV1 clock. The current J7200 clock data
has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
opposite of the actual implementation. Fix the data by simply adjusting
the register bit-shifts.

The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
register values, fix these as well.

Fixes: 277729eaf373 ("arm: mach-k3: Add platform data for j721e and j7200")
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
 arch/arm/mach-k3/j7200/clk-data.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Comments

Tom Rini Sept. 17, 2021, 10:53 p.m. UTC | #1 
On Tue, Sep 07, 2021 at 05:16:55PM -0500, Dave Gerlach wrote:

> From: Suman Anna <s-anna@ti.com>
> 
> The TI K3 Fractional PLLs use two programmable POSTDIV1 and POSTDIV2
> divisors to generate the final FOUTPOSTDIV clock. These are in sequence
> with POSTDIV2 following the POSTDIV1 clock. The current J7200 clock data
> has the POSTDIV2 clock as the parent for the POSTDIV1 clock, which is
> opposite of the actual implementation. Fix the data by simply adjusting
> the register bit-shifts.
> 
> The Main PLL1 POSTDIV clocks were also defined incorrectly using Main PLL0
> register values, fix these as well.
> 
> Fixes: 277729eaf373 ("arm: mach-k3: Add platform data for j721e and j7200")
> Signed-off-by: Suman Anna <s-anna@ti.com>
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/arch/arm/mach-k3/j7200/clk-data.c b/arch/arm/mach-k3/j7200/clk-data.c
index 93c067079ab6..49145bbfc8cd 100644
--- a/arch/arm/mach-k3/j7200/clk-data.c
+++ b/arch/arm/mach-k3/j7200/clk-data.c
@@ -319,8 +319,8 @@  static const struct clk_data clk_list[] = {
 	CLK_MUX("wkup_fref_clksel_out0", wkup_fref_clksel_out0_parents, 2, 0x43008050, 8, 1, 0),
 	CLK_MUX("main_pll_hfosc_sel_out1", main_pll_hfosc_sel_out1_parents, 2, 0x43008084, 0, 1, 0),
 	CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "main_pll_hfosc_sel_out1", 0x681000, 0, 1920000000),
-	CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x680038, 24, 3, 0),
-	CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
+	CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0),
+	CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0),
 	CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d00000, 0),
 	CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_1_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d01000, 0, 2400000000),
 	CLK_PLL_DEFFREQ("pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", "wkup_fref_clksel_out0", 0x40d02000, 0, 2000000000),
@@ -360,8 +360,8 @@  static const struct clk_data clk_list[] = {
 	CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout2_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d02088, 0, 7, 0),
 	CLK_DIV("hsdiv4_16fft_mcu_2_hsdivout3_clk", "pllfracf_ssmod_16fft_mcu_2_foutvcop_clk", 0x40d0208c, 0, 7, 0),
 	CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "main_pll_hfosc_sel_out0", 0x680000, 0),
-	CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 24, 3, 0),
-	CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 16, 3, 0),
+	CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0),
+	CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0),
 	CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "main_pll_hfosc_sel_out12", 0x68c000, 0),
 	CLK_PLL("pllfracf_ssmod_16fft_main_14_foutvcop_clk", "main_pll_hfosc_sel_out14", 0x68e000, 0),
 	CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "main_pll_hfosc_sel_out2", 0x682000, 0),