[v3,2/4] riscv: lib: introduce a cache_init interface

Add an interface for cache initialization. Each platform can overwrite
this weak function by their own implementation, such as sifive_cache in
this patch.

In sifive_cache, it invokes the generic cache_enable interface of cache
uclass to execute the relative implementation in SiFive ccache driver.

Signed-off-by: Zong Li <zong.li@sifive.com>
---
 arch/riscv/Kconfig             |  5 +++++
 arch/riscv/include/asm/cache.h |  1 +
 arch/riscv/lib/Makefile        |  1 +
 arch/riscv/lib/cache.c         |  5 +++++
 arch/riscv/lib/sifive_cache.c  | 27 +++++++++++++++++++++++++++
 5 files changed, 39 insertions(+)
 create mode 100644 arch/riscv/lib/sifive_cache.c

On 8/17/21 5:08 AM, Zong Li wrote:
> Add an interface for cache initialization. Each platform can overwrite
> this weak function by their own implementation, such as sifive_cache in
> this patch.
> 
> In sifive_cache, it invokes the generic cache_enable interface of cache
> uclass to execute the relative implementation in SiFive ccache driver.
> 
> Signed-off-by: Zong Li <zong.li@sifive.com>
> ---
>   arch/riscv/Kconfig             |  5 +++++
>   arch/riscv/include/asm/cache.h |  1 +
>   arch/riscv/lib/Makefile        |  1 +
>   arch/riscv/lib/cache.c         |  5 +++++
>   arch/riscv/lib/sifive_cache.c  | 27 +++++++++++++++++++++++++++
>   5 files changed, 39 insertions(+)
>   create mode 100644 arch/riscv/lib/sifive_cache.c
> 
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 4b0c3dffa6..ec651fe0a4 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT
>   	  The SiFive CLINT block holds memory-mapped control and status registers
>   	  associated with software and timer interrupts.
>   
> +config SIFIVE_CACHE
> +	bool
> +	help
> +	  This enables the operations to configure SiFive cache
> +
>   config ANDES_PLIC
>   	bool
>   	depends on RISCV_MMODE || SPL_RISCV_MMODE
> diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
> index ec8fe201d3..6ebb2b4329 100644
> --- a/arch/riscv/include/asm/cache.h
> +++ b/arch/riscv/include/asm/cache.h
> @@ -9,6 +9,7 @@
>   
>   /* cache */
>   void	cache_flush(void);
> +int cache_init(void);
>   
>   /*
>    * The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
> diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> index c4cc41434b..06020fcc2a 100644
> --- a/arch/riscv/lib/Makefile
> +++ b/arch/riscv/lib/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
>   obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
>   obj-$(CONFIG_CMD_GO) += boot.o
>   obj-y	+= cache.o
> +obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
>   ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
>   obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
>   obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
> diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
> index b1d42bcc2b..2cd66504c6 100644
> --- a/arch/riscv/lib/cache.c
> +++ b/arch/riscv/lib/cache.c
> @@ -70,3 +70,8 @@ __weak int dcache_status(void)
>   {
>   	return 0;
>   }
> +
> +__weak int cache_init(void)
> +{
> +	return 0;
> +}

Don't make this generic. Just call a `sifive_cache_init` or whatever.

IMO this pattern shouldn't be duplicated by other platforms, but it is OK to do for now until we have a more generic method.

--Sean

> diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c
> new file mode 100644
> index 0000000000..94e84e024e
> --- /dev/null
> +++ b/arch/riscv/lib/sifive_cache.c
> @@ -0,0 +1,27 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2021 SiFive, Inc
> + */
> +
> +#include <common.h>
> +#include <cache.h>
> +#include <dm.h>
> +
> +int cache_init(void)
> +{
> +	struct udevice *dev;
> +	int ret;
> +
> +	/* Enable ways of ccache */
> +	ret = uclass_get_device_by_driver(UCLASS_CACHE,
> +					  DM_DRIVER_GET(sifive_ccache),
> +					  &dev);
> +	if (ret)
> +		return log_msg_ret("Cannot enable cache ways", ret);
> +
> +	ret = cache_enable(dev);
> +	if (ret)
> +		return log_msg_ret("ccache enable failed", ret);
> +
> +	return 0;
> +}
>

On Tue, Aug 31, 2021 at 12:48 PM Sean Anderson <seanga2@gmail.com> wrote:
>
> On 8/17/21 5:08 AM, Zong Li wrote:
> > Add an interface for cache initialization. Each platform can overwrite
> > this weak function by their own implementation, such as sifive_cache in
> > this patch.
> >
> > In sifive_cache, it invokes the generic cache_enable interface of cache
> > uclass to execute the relative implementation in SiFive ccache driver.
> >
> > Signed-off-by: Zong Li <zong.li@sifive.com>
> > ---
> >   arch/riscv/Kconfig             |  5 +++++
> >   arch/riscv/include/asm/cache.h |  1 +
> >   arch/riscv/lib/Makefile        |  1 +
> >   arch/riscv/lib/cache.c         |  5 +++++
> >   arch/riscv/lib/sifive_cache.c  | 27 +++++++++++++++++++++++++++
> >   5 files changed, 39 insertions(+)
> >   create mode 100644 arch/riscv/lib/sifive_cache.c
> >
> > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> > index 4b0c3dffa6..ec651fe0a4 100644
> > --- a/arch/riscv/Kconfig
> > +++ b/arch/riscv/Kconfig
> > @@ -179,6 +179,11 @@ config SPL_SIFIVE_CLINT
> >         The SiFive CLINT block holds memory-mapped control and status registers
> >         associated with software and timer interrupts.
> >
> > +config SIFIVE_CACHE
> > +     bool
> > +     help
> > +       This enables the operations to configure SiFive cache
> > +
> >   config ANDES_PLIC
> >       bool
> >       depends on RISCV_MMODE || SPL_RISCV_MMODE
> > diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
> > index ec8fe201d3..6ebb2b4329 100644
> > --- a/arch/riscv/include/asm/cache.h
> > +++ b/arch/riscv/include/asm/cache.h
> > @@ -9,6 +9,7 @@
> >
> >   /* cache */
> >   void        cache_flush(void);
> > +int cache_init(void);
> >
> >   /*
> >    * The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
> > diff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile
> > index c4cc41434b..06020fcc2a 100644
> > --- a/arch/riscv/lib/Makefile
> > +++ b/arch/riscv/lib/Makefile
> > @@ -10,6 +10,7 @@ obj-$(CONFIG_CMD_BOOTM) += bootm.o
> >   obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o
> >   obj-$(CONFIG_CMD_GO) += boot.o
> >   obj-y       += cache.o
> > +obj-$(CONFIG_SIFIVE_CACHE) += sifive_cache.o
> >   ifeq ($(CONFIG_$(SPL_)RISCV_MMODE),y)
> >   obj-$(CONFIG_$(SPL_)SIFIVE_CLINT) += sifive_clint.o
> >   obj-$(CONFIG_ANDES_PLIC) += andes_plic.o
> > diff --git a/arch/riscv/lib/cache.c b/arch/riscv/lib/cache.c
> > index b1d42bcc2b..2cd66504c6 100644
> > --- a/arch/riscv/lib/cache.c
> > +++ b/arch/riscv/lib/cache.c
> > @@ -70,3 +70,8 @@ __weak int dcache_status(void)
> >   {
> >       return 0;
> >   }
> > +
> > +__weak int cache_init(void)
> > +{
> > +     return 0;
> > +}
>
> Don't make this generic. Just call a `sifive_cache_init` or whatever.
>
> IMO this pattern shouldn't be duplicated by other platforms, but it is OK to do for now until we have a more generic method.
>

Hi Sean,
I have sent the v4 patch to use generic enable_caches hook, it seems
to me that we could add an additional arch-defined interface in the
future if we really needed it, rather than at this time. Please help
me to review the v4 patch and hope we are on the same page.

> --Sean
>
> > diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c
> > new file mode 100644
> > index 0000000000..94e84e024e
> > --- /dev/null
> > +++ b/arch/riscv/lib/sifive_cache.c
> > @@ -0,0 +1,27 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (C) 2021 SiFive, Inc
> > + */
> > +
> > +#include <common.h>
> > +#include <cache.h>
> > +#include <dm.h>
> > +
> > +int cache_init(void)
> > +{
> > +     struct udevice *dev;
> > +     int ret;
> > +
> > +     /* Enable ways of ccache */
> > +     ret = uclass_get_device_by_driver(UCLASS_CACHE,
> > +                                       DM_DRIVER_GET(sifive_ccache),
> > +                                       &dev);
> > +     if (ret)
> > +             return log_msg_ret("Cannot enable cache ways", ret);
> > +
> > +     ret = cache_enable(dev);
> > +     if (ret)
> > +             return log_msg_ret("ccache enable failed", ret);
> > +
> > +     return 0;
> > +}
> >